Abstract: A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed. Thereby, a trench is formed over the via hole.

Abstract: A method for forming an amino-free low k material. The method includes steps of introducing an amino-free gas into a chemical vapor deposition reactor; and decomposing the gas to form a layer of low k material. The amino-free gas is comprised of silane-based gas and CO2. O2 is also applicable as the process gas.

Abstract: A method for improving adhesion of a low k dielectric to a barrier layer. A substrate covered by an insulating layer having copper interconnects is provided. A sealing layer is formed on the copper interconnects and the insulating layer. A plasma treatment is performed on the sealing layer by a reaction gas including at least one of CO2, NH3, NO2, SiH4, trimethylsilane, and tetramethylsilane. A low k dielectric layer is formed on the sealing layer.

Abstract: A method of forming a sealing layer on a copper pattern. First, a semiconductor substrate having a copper pattern is provided. Then, a tantalum layer is deposited on the upper surface of the copper pattern by atomic layer chemical vapor deposition (ALCVD). Nitrogen gas is then introduced to react with the upmost atomic layer of the tantalum layer so as to form a sealing layer comprising tantalum nitride.

Abstract: A method to reduce reflectivity of polysilicon layer. First, a semiconductor substrate is provided. The semiconductor substrate is placed in a single-wafer CVD chamber. Then, a silane-containing gas is introduced into the single-wafer CVD chamber to form a polysilicon layer on the semiconductor substrate. Next, hydrogen gas is introduced into the single-wafer CVD chamber to adjust the grain size of the upper surface of the polysilicon layer. Then, oxygen gas is introduced into the single-wafer CVD chamber to form a silicon oxide film on the polysilicon layer.

Abstract: A method for improving adhesion of a low k dielectric to a barrier layer. A substrate covered by an insulating layer having copper interconnects is provided. A sealing layer is formed on the copper interconnects and the insulating layer. A plasma treatment is performed on the sealing layer by a reaction gas including at least one of CO2, NH3, NO2, SiH4, trimethylsilane, and tetramethylsilane. A low k dielectric layer is formed on the sealing layer.

Abstract: A method of fabricating a dual damascene structure on a semiconductor substrate having a conductive structure. First, a deposited dielectric layer, a spin-coated dielectric layer, and a hard mask with a via opening are sequentially formed on the semiconductor substrate. Then, a photoresist pattern having a trench opening is formed on the hard mask. The spin-coated dielectric layer is etched through the via opening while the hard mask is used as the etching mask. Next, the hard mask is etched using the photoresist pattern as the etching mask to create a damascene opening including the via opening and the trench opening. The spin-coated dielectric layer and the deposited dielectric layer are then etched through the damascene opening to form a dual damascene structure to expose the conductive structure.

Abstract: A capacitor in which the lower electrode and an interconnect line are located at the same level. The capacitor includes a first conductive line and a second conductive line on a substrate located at the same level, wherein the second conductive line defines a capacitor region and is used as a lower electrode of the capacitor; an insulating layer on the substrate, the first conductive line, and the second conductive line; and a third conductive line on the insulating layer in the capacitor region such that the third conductive line is used as an upper electrode of the capacitor. Since the lower electrode and an interconnect line can be in-situ (concurrently) formed to be located at the same level, one mask can be omitted compared with the conventional method, and production costs can be reduced.

Abstract: A method of forming an identifying mark on a semiconductor wafer. The identifying mark, for example a bar code or a character of patterns or words, is formed on the side wall of the semiconductor wafer to avoid contamination and the creation of failure dies during the formation of the identifying mark.

Abstract: A dual damascene process for improving planarization of an inter-metal dielectric (IMD) layer. A removable protective layer is provided between a hard mask layer and an IMD layer to prevent the top of the IMD layer from erosion by dry etching during the formation of a dual damascene opening. After using an organic solution to remove the removable protective layer, the top of the IMD layer becomes a planarized surface.

Abstract: A method of forming a stacked dielectric layer on a semiconductor substrate having metal patterns. A first dielectric layer is formed on the semiconductor substrate. Next, a second dielectric layer is formed on the first dielectric layer to generate a composite dielectric layer. The second dielectric layer has a dielectric constant (k) higher than that of the first dielectric layer, a hardness higher than that of the first dielectric layer, and a thickness less than that of the first dielectric layer. The steps of forming the first dielectric layer and second dielectric layer can be repeated at least 2 to 3 times to form a stacked dielectric layer.

Abstract: A method of forming a shallow trench isolation has the steps of: forming a plurality of trenches in a semiconductor substrate; forming an oxide liner on the bottom and sidewall of each trench; and thermal annealing in a nitrogen-containing atmosphere to dope nitrogen elements in the oxide liner. Thus, a nitrogen-rich layer is formed at the interface between the oxide liner and the semiconductor substrate.

Abstract: A method of fabricating a shallow trench isolation. The oxide layer is treated by a nitrogen-based compound. After treatment, the oxide layer plays not only the role of the etching mask during shallow trench isolation formation, but also of the stop layer during chemical mechanical polishing. Therefore, the selectivity of the chemical mechanical polishing is enhanced.

Abstract: A method of forming an oxide film with resistance to erosion caused by a stripper during removal of a photoresist layer. First, a substrate is provided with a polysilicon gate layer. Then, using LPCVD, an LP-oxide film is formed on the substrate to cover the polysilicon gate layer. Then, using annealing treatment with a gas containing a nitrogen element, a surface layer with an oxynitride composition is formed on the oxide film.

Abstract: A method of forming a polysilicon to polysilicon capacitor on a substrate, wherein the substrate has an insulating area and an active area and is covered by a first insulating layer. First, a first conductive layer, a second insulating layer and a second conductive layer are formed on the first insulating layer in sequence. Next, the second conductive layer and the second insulating layer are etched in sequence to form a top plate and a dielectric layer on the first conductive layer. Finally, the first conductive layer and the first insulating layer are etched to form a bottom plate over the insulating area and a gate structure over the active area.

Abstract: A method of fabricating an IMD layer is provided on a semiconductor substrate, on which at least two adjacent metal wiring lines separated by a gap are patterned. A first dielectric layer, preferably of silicon oxide, is formed on the metal wiring lines to partially fill the gap below the level of the top of the metal wiring lines using high density plasma chemical vapor deposition (HDPCVD). Then, a second dielectric layer, preferably of silicon oxide, is formed on the first dielectric layer to completely fill the gap to a predetermined thickness using PECVD. Thus, the first dielectric layer and the second dielectric layer between the two adjacent metal wiring lines serve as the IMD layer.

Abstract: An interconnect structure has at least two adjacent metal wiring lines patterned on a semiconductor substrate and separated by a gap. A dielectric layer is formed on the metal wiring lines to fill the gap to a predetermined thickness. A metallic barrier layer, which may be of Ti, TiN, Ta, TaN, Cu or copper alloys are sandwiched between the sidewall of the metal wiring line and the dielectric layer. In addition, a contact plug passing through the dielectric layer is electrically connected to the top of the metal wiring line.

Abstract: An interconnect structure comprises a first level metal wiring line patterned on a semiconductor substrate, an inter-metal dielectric (IMD) layer formed on the metal wiring line, a contact plug passing through the IMD layer and electrically connected to the top of the first level metal wiring line, and a second level metal wiring line patterned on the IMD layer and electrically connected to the top of the contact plug. A cap layer is sandwiched between the top of the IMD layer and the bottom of the second level metal wiring line.

Abstract: A method of reducing micro-scratches during tungsten CMP. Tungsten CMP with a standard tungsten slurry is first provided on the exposed surfaces of a tungsten plug and a IMD layer on a semiconductor substrate. The tungsten CMP with an oxide slurry is then provided on the polished surfaces of the tungsten plugs and the IMD layer.

Abstract: An organic copper diffusion barrier layer having low dielectric constant is provided. The organic copper diffusion barrier layer can be applied to a dual damascene structure, which is formed between a copper wiring layer and an organic dielectric layer, to defend copper diffusion from the copper wiring layer into the organic dielectric layer. The organic copper diffusion barrier layer includes a benzocyclo polymer, which it has a benzene ring functional group that can catch copper and prevent copper diffusing into the organic dielectric layer. The problem of thermal diffusion and electro-migration can be avoided.