Patents by Inventor Si-Young Choi

Si-Young Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210076135
    Abstract: A display device includes a display panel including a main area, a first subsidiary area extending from a first side of the main area, and a second subsidiary area extending from a second side of the main area, and a first sound generator disposed on the first subsidiary area and the second subsidiary area of the display panel, where the first sound generator generates a sound by vibrating the first subsidiary area and the second subsidiary area of the display panel.
    Type: Application
    Filed: May 18, 2020
    Publication date: March 11, 2021
    Inventors: Si Young CHOI, Young Sik KIM, Jeong Heon LEE
  • Publication number: 20210061930
    Abstract: The present disclosure relates to a method for preparing a polyolefin using a supported hybrid metallocene catalyst. According to the present disclosure, a polyolefin having a narrow molecular weight distribution can be prepared very effectively by introducing a cocatalyst in an optimum conent in the presence of a supported hybrid metallocene catalyst containing two or more metallocene compounds having a specific chemical structure. The polyolefin prepared according to the present disclosure exhibits excellent uniformity in chlorine distribution in polyolefin during chlorination, thereby significantly improving elongation of the chlorinated polyolefin, compatibility with PVC and impact reinforcing performance. Thus, it exhibits excellent chemical resistance, weather resistance, flame retardancy, processability and impact strength reinforcing effect, and can be suitably applied as an impact reinforcing agent for PVC pipes and window profiles.
    Type: Application
    Filed: January 9, 2019
    Publication date: March 4, 2021
    Applicant: LG Chem, Ltd.
    Inventors: Bog Ki Hong, Jin Young Park, Si Jung Lee, Yi Young Choi, Soung Hun Yoo, Sunghyun Park, Chang Woan Han, Sun Mi Kim
  • Publication number: 20210047443
    Abstract: A polyethylene according to the present disclosure maintains a stable crystal structure at a high temperature and ensures excellent uniformity in chlorine distribution, thereby preparing a chlorinated polyethylene having excellent chlorination productivity and thermal stability by reacting with chlorine, and may also prepare a PVC compound with improved impact strength by including the chlorinated polyethylene.
    Type: Application
    Filed: December 10, 2019
    Publication date: February 18, 2021
    Applicant: LG Chem, Ltd.
    Inventors: Cheolhwan Jeong, Si Jung Lee, Bog Ki Hong, Sunghyun Park, Sun Mi Kim, Yi Young Choi
  • Publication number: 20210048842
    Abstract: According to one aspect of the invention, a circuit board for a display device includes: a first layer; a first lead line disposed on the first layer; and a sound generator disposed on the first layer, and the sound generator including: a first electrode to receive a first driving voltage; a second electrode to receive a second driving voltage; and a second layer disposed between the first electrode and the second electrode to contract or expand according to the first driving voltage and the second driving voltage; and a first solder to electrically communicate the first lead line and the first electrode.
    Type: Application
    Filed: June 2, 2020
    Publication date: February 18, 2021
    Inventors: Si Young Choi, Jong Tae Kim, Young Sik Kim, Sang Wook Yoo, Jeong Heon Lee
  • Publication number: 20210039506
    Abstract: An electric power conversion system includes: an AC-DC conversion circuit converting AC charging power into DC power; a motor including a plurality of coils, one end of each being connected to a neutral point; a first switching device selectively allowing or blocking supply of output power from the AC-DC conversion circuit to the neutral point; an inverter including a plurality of motor connection terminals connected to the other ends of the coils of the motor, respectively, DC connection terminals including a positive terminal and a negative terminal, and a plurality of switching elements forming electrical connections between the DC connection terminals and the plurality of motor connection terminals; a battery connected to the DC connection terminals of the inverter; and a controller controlling operations of the AC-DC conversion circuit, the first switching device, and the inverter in accordance with whether or not the battery is charged.
    Type: Application
    Filed: March 11, 2020
    Publication date: February 11, 2021
    Applicants: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Dae Woo LEE, Min Seong CHOI, Si Hun YANG, Jae Eun CHA, Jin Young YANG, In Yong YEO
  • Patent number: 10904790
    Abstract: The present disclosure provides methods and apparatus relating to a 5G or pre-5G communication system for supporting a higher data rate than that of a 4G communication system, such as long term evolution (LTE). A method for processing traffic at a core network entity processes traffic includes transmitting a message for requesting assistance information to at least one base station, receiving the assistance information from the at least one base station, splitting the traffic based on the received assistance information, and transmitting the split traffic through a core network. A core network entity includes a transceiver and a processor configured to control the transceiver to transmit a message for requesting assistance information to at least one base station, receive the assistance information from the at least one base station, split traffic based on the received assistance information, and transmit data through the split traffic.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 26, 2021
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: Hyung-Ho Lee, Sae-Woong Bahk, Si-Young Choi, Seong-Joon Kang, Dong-Yeon Woo
  • Publication number: 20200143533
    Abstract: A method of analyzing a perovskite structure using machine learning, the method comprising the steps of: (a) obtaining an atomic image using an atomic structure simulator; (b) making a CNN model learn the atomic image; and (c) obtaining an atomic image of an actual substance using a TEM or a STEM and then applying the image to the learnt CNN model.
    Type: Application
    Filed: September 27, 2019
    Publication date: May 7, 2020
    Inventors: Si-Young CHOI, Gi-Yeop KIM, Kyoung-June KO, Jin-Hyuk JANG
  • Patent number: 10640774
    Abstract: The present invention relates to a recombinant microorganism having the ability to produce poly(lactate-co-glycolate) and its copolymers from xylose, and more particularly to a recombinant microorganism having the ability to produce poly(lactate-co-glycolate) and its copolymers without having to supply a glycolate precursor from an external source, and a method of producing a poly(lactate-co-glycolate) copolymers using the same.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: May 5, 2020
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Sang Yup Lee, So Young Choi, Si Jae Park
  • Patent number: 10431530
    Abstract: A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located on the substrate, a lead frame located on the substrate and including first, second, third, and fourth bodies; a first terminal connected to the first body, a second terminal connected to the second body, and a third common terminal that connects the third body and the fourth body, wherein a length of the third common terminal is longer than that of the first and second terminals.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: October 1, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Sik Choi, Si Hyeon Go, Jun Young Heo, Moon Taek Sung, Dong Seong Oh
  • Publication number: 20190037443
    Abstract: The present disclosure provides methods and apparatus relating to a 5G or pre-5G communication system for supporting a higher data rate than that of a 4G communication system, such as long term evolution (LTE). A method for processing traffic at a core network entity processes traffic includes transmitting a message for requesting assistance information to at least one base station, receiving the assistance information from the at least one base station, splitting the traffic based on the received assistance information, and transmitting the split traffic through a core network. A core network entity includes a transceiver and a processor configured to control the transceiver to transmit a message for requesting assistance information to at least one base station, receive the assistance information from the at least one base station, split traffic based on the received assistance information, and transmit data through the split traffic.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 31, 2019
    Inventors: Hyung-Ho LEE, Sae-Woong BAHK, Si-Young CHOI, Seong-Joon KANG, Dong-Yeon WOO
  • Patent number: 9627542
    Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: April 18, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung-Ho Kwon, Cheol Kim, Ho-Young Kim, Se-Jung Park, Myeong-Cheol Kim, Bo-Kyeong Kang, Bo-Un Yoon, Jae-Kwang Choi, Si-Young Choi, Suk-Hoon Jeong, Geum-Jung Seong, Hee-Don Jeong, Yong-Joon Choi, Ji-Eun Han
  • Patent number: 9431341
    Abstract: Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate. A through-silicon-via and/or a pad can be directly bonded to another through-silicon-via and/or another pad by applying pressure only, and without performing a heat process.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: August 30, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yi-Koan Hong, Byung-Lyul Park, Ji-Soon Park, Si-Young Choi
  • Publication number: 20160247925
    Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
    Type: Application
    Filed: May 2, 2016
    Publication date: August 25, 2016
    Inventors: Byoung-Ho KWON, Cheol KIM, Ho-Young KIM, Se-Jung PARK, Myeong-Cheol KIM, Bo-Kyeong KANG, Bo-Un YOON, Jae-Kwang CHOI, Si-Young CHOI, Suk-Hoon JEONG, Geum-Jung SEONG, Hee-Don JEONG, Yong-Joon CHOI, Ji-Eun HAN
  • Publication number: 20160064380
    Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
    Type: Application
    Filed: November 5, 2015
    Publication date: March 3, 2016
    Inventors: Byoung-Ho KWON, Cheol KIM, Ho-Young KIM, Se-Jung PARK, Myeong-Cheol KIM, Bo-Kyeong KANG, Bo-Un YOON, Jae-Kwang CHOI, Si-Young CHOI, Suk-Hoon JEONG, Geum-Jung SEONG, Hee-Don JEONG, Yong-Joon CHOI, Ji-Eun HAN
  • Patent number: 9190495
    Abstract: A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: November 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Do Ryu, Dong-Chan Kim, Seong-Hoon Jeong, Si-Young Choi, Yu-Gyun Shin, Tai-Su Park, Jong-Ryeol Yoo, Jong-Hoon Kang
  • Patent number: 9190407
    Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: November 17, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung-Ho Kwon, Cheol Kim, Ho-Young Kim, Se-Jung Park, Myeong-Cheol Kim, Bo-Kyeong Kang, Bo-Un Yoon, Jae-Kwang Choi, Si-Young Choi, Suk-Hoon Jeong, Geum-Jung Seong, Hee-Don Jeong, Yong-Joon Choi, Ji-Eun Han
  • Publication number: 20150137325
    Abstract: Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate. A through-silicon-via and/or a pad can be directly bonded to another through-silicon-via and/or another pad by applying pressure only, and without performing a heat process.
    Type: Application
    Filed: July 11, 2014
    Publication date: May 21, 2015
    Inventors: Yi-Koan HONG, Byung-Lyul PARK, Ji-Soon PARK, Si-Young CHOI
  • Publication number: 20150097251
    Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
    Type: Application
    Filed: December 12, 2014
    Publication date: April 9, 2015
    Inventors: Byoung-Ho KWON, Cheol KIM, Ho-Young KIM, Se-Jung PARK, Myeong-Cheol KIM, Bo-Kyeong KANG, Bo-Un YOON, Jae-Kwang CHOI, Si-Young CHOI, Suk-Hoon JEONG, Geum-Jung SEONG, Hee-Don JEONG, Yong-Joon CHOI, Ji-Eun HAN
  • Publication number: 20150076617
    Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.
    Type: Application
    Filed: November 20, 2014
    Publication date: March 19, 2015
    Inventors: Myeong-Cheol Kim, Il-Sup Kim, Cheol Kim, Jong-Chan Shin, Jong-Wook Lee, Choong-Ho Lee, Si-Young Choi, Jong-Seo Hong
  • Patent number: 8916460
    Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: December 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Ho Kwon, Cheol Kim, Ho-Young Kim, Se-Jung Park, Myeong-Cheol Kim, Bo-Kyeong Kang, Bo-Un Yoon, Jae-Kwang Choi, Si-Young Choi, Suk-Hoon Jeong, Geum-Jung Seong, Hee-Don Jeong, Yong-Joon Choi, Ji-Eun Han