Patents by Inventor Siamack Nemazie

Siamack Nemazie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190265889
    Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
    Type: Application
    Filed: May 14, 2019
    Publication date: August 29, 2019
    Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie
  • Publication number: 20190235757
    Abstract: A non-volatile memory device configured to emulate DRAM interface comprising a memory array that includes a plurality of magnetic memory cells organized into rows and columns with at least one row of the magnetic memory cells comprising one or more pages that store data during a burst write operation; a control circuit operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 1, 2019
    Inventor: Siamack Nemazie
  • Patent number: 10331351
    Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie
  • Patent number: 10268393
    Abstract: A non-volatile memory device configured to emulate DRAM interface comprising a memory array that includes a plurality of magnetic memory cells organized into rows and columns with at least one row of the magnetic memory cells comprising one or more pages that store data during a burst write operation; a control circuit; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array. The control circuit is operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; and after receiving one or more data units of the data by the memory array, allow a subsequent burst write or read command to begin before completion of the burst write operation in progress.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: April 23, 2019
    Assignee: Avalanche Technology, Inc.
    Inventor: Siamack Nemazie
  • Patent number: 10101924
    Abstract: A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the one or more SSDs and creating a NVMe command structure for each sub-command.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: October 16, 2018
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • Publication number: 20180275922
    Abstract: A Solid State Disk (SSD) is disclosed to avoid collision of page reads with page program or block erase and thereby provide consistent latency. In one embodiment a group of NVM dies are paired, information programmed only in dies that are paired, and programmed in both dies of the pair, concurrent program or erase of paired dies are avoided, and read from a die that is being programmed or erased is directed to its paired die that is not being programmed or erased.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 27, 2018
    Inventor: Siamack Nemazie
  • Patent number: 10078449
    Abstract: A memory device has a plurality of dedicated data blocks for storing user data and a plurality of dedicated overhead blocks for storing overhead data. A dedicated overhead block of the plurality of dedicated overhead blocks has a plurality of overhead segments. The overhead segments have physical block address registers configured to store physical block addresses defining respective dedicated data blocks.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: September 18, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Petro Estakhri, Siamack Nemazie
  • Patent number: 10042758
    Abstract: A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: August 7, 2018
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie, Anilkumar Mandapuram
  • Patent number: 10037272
    Abstract: A storage system includes a central processing unit (CPU) subsystem including a CPU, a physically-addressed solid state disk (SSD) that is addressable using physical addresses associated with user data, provided by the CPU, to be stored in or retrieved from the physically-addressed SSD in blocks. Further, the storage system includes a non-volatile memory module, the non-volatile memory module having flash tables used to manage blocks in the physically addressed SSD, the flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. Additionally, the storage system includes a peripheral component interconnect express (PCIe) switch coupled to the CPU subsystem and a network interface controller coupled through a PCIe bus to the PCIe switch, wherein the flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 31, 2018
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie, Anilkumar Mandapuram
  • Publication number: 20180088808
    Abstract: A non-volatile memory device configured to emulate DRAM interface comprising a memory array that includes a plurality of magnetic memory cells organized into rows and columns with at least one row of the magnetic memory cells comprising one or more pages that store data during a burst write operation; a control circuit; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array. The control circuit is operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; and after receiving one or more data units of the data by the memory array, allow a subsequent burst write or read command to begin before completion of the burst write operation in progress.
    Type: Application
    Filed: November 17, 2017
    Publication date: March 29, 2018
    Inventor: Siamack Nemazie
  • Patent number: 9898204
    Abstract: A memory device configured to emulate DRAM comprising a memory array that includes a plurality of memory cells organized into rows and columns with at least one row of memory cells comprising one or more pages that store data during a burst write operation; a control circuit; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array. The control circuit is operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; and after receiving one or more data units of the data by the memory array, allow a subsequent burst write or read command to begin before completion of the burst write operation in progress.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: February 20, 2018
    Assignee: Avalanche Technology, Inc.
    Inventor: Siamack Nemazie
  • Patent number: 9830106
    Abstract: The present invention is directed to a storage device including a storage media and a controller coupled thereto through a high speed interface. The storage media includes one or more byte-addressable persistent memory devices, one or more block-addressable persistent memory devices, a hybrid reserved area spanning at least a portion of the one or more byte-addressable persistent memory devices, and a hybrid user area spanning at least a portion of the one or more block-addressable persistent memory devices. The controller uses the hybrid reserved area to store private data. Each of the one or more byte-addressable persistent memory devices may include one or more magnetic random access memory (MRAM) arrays. Each of the one or more block-addressable persistent memory devices may include one or more NAND flash memory arrays. The high speed interface may be a universal flash storage (UFS) interface that operates in the full-duplex mode.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: November 28, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Ngon Van Le, Berhanu Iman, Siamack Nemazie, Ravishankar Tadepalli
  • Patent number: 9824050
    Abstract: A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: November 21, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Anilkumar Mandapuram, Siamack Nemazie
  • Patent number: 9792047
    Abstract: A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the SSDs independently of the command thereby causing striping across the SSDs.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: October 17, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • Patent number: 9792073
    Abstract: A method of managing logical unit numbers (LUNs) in a storage system includes identifying one or more LUN logical block address (LBA)-groups being affected. The one or more LUN LBA-groups defining a LUN. The method further determining the existence of an association of each of the affected LUN LBA-groups to a portion of a storage pool and maintaining a mapping table to track the association of the LUN LBA-groups to the storage pool.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: October 17, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie, Ruchirkumar D. Shah
  • Publication number: 20170255386
    Abstract: A memory device configured to emulate DRAM comprising a memory array that includes a plurality of memory cells organized into rows and columns with at least one row of memory cells comprising one or more pages that store data during a burst write operation; a control circuit; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array. The control circuit is operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; and after receiving one or more data units of the data by the memory array, allow a subsequent burst write or read command to begin before completion of the burst write operation in progress.
    Type: Application
    Filed: May 19, 2017
    Publication date: September 7, 2017
    Inventor: Siamack Nemazie
  • Patent number: 9727245
    Abstract: In accordance with a method of the invention, host data, accompanied by host LBA, is received from a host. If the host data is determined not to be a duplicate host data, an available intermediate LBA (iLBA) is identified and the host LBA is linked to the identified iLBA. During writing of the received host data to the SSDs, an available SLBA is identified and saved to a table at a location indexed by the identified iLBA. Accordingly, the next time the same host data is received, it is recognized as a duplicate host data and the host address accompanying it is linked to the same iLBA, which is already associated with the same SLBA. Upon this recognition, an actual write to the SSDs is avoided.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: August 8, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Siamack Nemazie, Mehdi Asnaashari, Ruchirkumar D. Shah
  • Patent number: 9658780
    Abstract: A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: May 23, 2017
    Assignee: Avalanche Technology, Inc.
    Inventor: Siamack Nemazie
  • Patent number: 9652386
    Abstract: An embodiment of the present invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array and NAND array and a hybrid user area made of a combination of MRAM array and NAND array. The mass storage device further includes a controller with a host interface and a flash interface coupled to the MRAM and NAND flash memory devices through the flash interface.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: May 16, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • Publication number: 20170131943
    Abstract: The present invention is directed to a storage device including a storage media and a controller coupled thereto through a high speed interface. The storage media includes one or more byte-addressable persistent memory devices, one or more block-addressable persistent memory devices, a hybrid reserved area spanning at least a portion of the one or more byte-addressable persistent memory devices, and a hybrid user area spanning at least a portion of the one or more block-addressable persistent memory devices. The controller uses the hybrid reserved area to store private data. Each of the one or more byte-addressable persistent memory devices may include one or more magnetic random access memory (MRAM) arrays. Each of the one or more block-addressable persistent memory devices may include one or more NAND flash memory arrays. The high speed interface may be a universal flash storage (UFS) interface that operates in the full-duplex mode.
    Type: Application
    Filed: January 20, 2017
    Publication date: May 11, 2017
    Inventors: Ngon Van Le, Berhanu Iman, Siamack Nemazie, Ravishankar Tadepalli