Patents by Inventor Siamack Nemazie

Siamack Nemazie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160328152
    Abstract: A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.
    Type: Application
    Filed: July 18, 2016
    Publication date: November 10, 2016
    Inventor: Siamack Nemazie
  • Publication number: 20160232092
    Abstract: An embodiment of the present invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array and NAND array and a hybrid user area made of a combination of MRAM array and NAND array. The mass storage device further includes a controller with a host interface and a flash interface coupled to the MRAM and NAND flash memory devices through the flash interface.
    Type: Application
    Filed: April 8, 2016
    Publication date: August 11, 2016
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • Publication number: 20160231943
    Abstract: A memory device has a plurality of dedicated data blocks for storing user data and a plurality of dedicated overhead blocks for storing overhead data. A dedicated overhead block of the plurality of dedicated overhead blocks has a plurality of overhead segments. The overhead segments have physical block address registers configured to store physical block addresses defining respective dedicated data blocks.
    Type: Application
    Filed: April 21, 2016
    Publication date: August 11, 2016
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Petro Estakhri, Siamack Nemazie
  • Patent number: 9396783
    Abstract: A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: July 19, 2016
    Assignee: Avalanche Technology, Inc.
    Inventor: Siamack Nemazie
  • Patent number: 9384127
    Abstract: A memory device has a plurality of dedicated data blocks for storing user data and a plurality of dedicated overhead blocks for storing overhead data. A dedicated overhead block of the plurality of dedicated overhead blocks has a plurality of overhead segments. The overhead segments have physical block address registers configured to store physical block addresses defining respective dedicated data blocks.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: July 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Petro Estakhri, Siamack Nemazie
  • Publication number: 20160148667
    Abstract: A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.
    Type: Application
    Filed: January 28, 2016
    Publication date: May 26, 2016
    Inventor: Siamack Nemazie
  • Patent number: 9319387
    Abstract: A magnetic memory device includes a main memory made of magnetic memory, the main memory and further includes a parameter area used to store parameters used to authenticate data. Further, the magnetic memory device has parameter memory that maintains a protected zone used to store protected zone parameters, and an authentication zone used to store authentication parameters, the protection zone parameters and the authentication parameters being associated with the data that requires authentication. Upon modification of any of the parameters stored in the parameter memory by a user, a corresponding location of the parameter area of the main memory is also modified.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: April 19, 2016
    Assignee: Avalanche Technology, Inc.
    Inventors: Siamack Nemazie, Ngon Van Le
  • Patent number: 9311232
    Abstract: An embodiment of the invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array NAND array and hybrid user area made of a combination of MRAM array and NAND array and further includes a controller with a host interface and flash interface coupled to the MRAM and NAND flash memory devices through a flash interface.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: April 12, 2016
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • Publication number: 20160085705
    Abstract: A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table.
    Type: Application
    Filed: November 20, 2015
    Publication date: March 24, 2016
    Inventors: Anilkumar Mandapuram, Siamack Nemazie
  • Patent number: 9251059
    Abstract: A storage system includes one or more RAID groups, a RAID group comprising a number of physically addressed solid state disks (paSSD). Stripes are formed across a RAID group, data to be written is saved in a non-volatile buffer until enough data for a full strip is received (without any restriction about logical address of data), full stripes are sent and written to paSSDs comprising the RAID group, accordingly the partial stripe read-modify-write is avoided.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: February 2, 2016
    Assignee: Avalanche Technology, Inc.
    Inventors: Siamack Nemazie, Ngon Van Le, Anilkumar Mandapuram
  • Patent number: 9251882
    Abstract: A memory device includes a magnetic memory unit for storing a burst of data during burst write operations, each burst of data includes, sequential data units with each data unit being received at a clock cycle, and written during a burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data, furthermore the memory device allowing burst write operation to begin while receiving data units of the next burst of data to be written or providing read data.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: February 2, 2016
    Assignee: Avalanche Technology, Inc.
    Inventor: Siamack Nemazie
  • Publication number: 20160021073
    Abstract: A magnetic memory device includes a main memory made of magnetic memory, the main memory and further includes a parameter area used to store parameters used to authenticate data. Further, the magnetic memory device has parameter memory that maintains a protected zone used to store protected zone parameters, and an authentication zone used to store authentication parameters, the protection zone parameters and the authentication parameters being associated with the data that requires authentication. Upon modification of any of the parameters stored in the parameter memory by a user, a corresponding location of the parameter area of the main memory is also modified.
    Type: Application
    Filed: September 28, 2015
    Publication date: January 21, 2016
    Applicant: AVALANCHE TECHNOLOGY, INC.
    Inventors: Siamack Nemazie, NGON VAN LE
  • Patent number: 9229892
    Abstract: A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: January 5, 2016
    Assignee: AVALANCHE TECHNOLOGY, INC.
    Inventors: Anilkumar Mandapuram, Siamack Nemazie
  • Publication number: 20150378886
    Abstract: Flash geometry information of the solid state disk (SSD) is maintained as is a logically-addressable SSD (laSSD) geometry information of the SSD. Based on the flash geometry and the laSSD geometry, virtual super blocks are configured by dynamically binding logical SSD logical block addresses (SLBAs) of a virtual super block with a physical super block within the laSSD. A virtual super block is made of a number of virtual blocks and each virtual block made of a number of virtual pages. Each of the virtual blocks corresponds to a physical block of a physical super block within the laSSD such that the virtual pages of the virtual block correspond to like physical pages of a corresponding physical block. Host logical block addresses (LBAs) are assigned to laSSD LBAs (SLBAs), which identify the virtual super blocks used for striping across physical super blocks.
    Type: Application
    Filed: April 6, 2015
    Publication date: December 31, 2015
    Inventors: Siamack Nemazie, Mehdi Asnaashari, Ruchirkumar D. Shah
  • Publication number: 20150378884
    Abstract: In accordance with various embodiments of the invention, the storage processor 10, rather than the storage pool 26, determines locations within the storage pool 26 into which data from the host 12 is to be stored by controlling striping across the SSDs of the storage pool 26 thereby increasing performance of the overall system, i.e. storage system 10, storage pool 26 and host 12. Performance improvement is realized over that of prior art systems because the storage system 10 has a global view of data traffic of the overall system and is aware of what is going on with the overall system as opposed to the SSDs of the storage pool 26, which have comparatively limited view. In accordance with a method and apparatus of the invention, an exemplary manner in which the storage system 10 is capable of controlling addressing of the SSDs of the storage pool 26 is by maintaining geometry information of the SSDs in the memory 20 and maintaining virtual super blocks associated with the SSDs.
    Type: Application
    Filed: April 6, 2015
    Publication date: December 31, 2015
    Inventors: Siamack Nemazie, Mehdi Asnaashari, Ruchirkumar D. Shah
  • Patent number: 9224504
    Abstract: A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: December 29, 2015
    Assignee: AVALANCHE TECHNOLOGY, INC.
    Inventors: Siamack Nemazie, Ebrahim Abedifard
  • Patent number: 9213495
    Abstract: A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: December 15, 2015
    Assignee: AVALANCHE TECHNOLOGY, INC.
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • Patent number: 9195604
    Abstract: Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: November 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Siamack Nemazie, Farshid Tabrizi, Berhanu Iman, Ruchir Shah, William E. Benson, Michael George
  • Patent number: 9165653
    Abstract: The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data from memory cells corresponding to a sector of data, determining a number of the memory cells in a non-erased state, and, if the number of the memory cells in a non-erased state is less than or equal to a number of errors correctable by an ECC engine, determining the sector is erased.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mehdi Asnaashari, Yu-Song Liao, Siamack Nemazie
  • Patent number: 9158623
    Abstract: A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: October 13, 2015
    Assignee: AVALANCHE TECHNOLOGY, INC.
    Inventors: Siamack Nemazie, Anilkumar Mandapuram