Patents by Inventor Siegmar Koeppe
Siegmar Koeppe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8854866Abstract: A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.Type: GrantFiled: June 17, 2011Date of Patent: October 7, 2014Assignee: Infineon Technologies AGInventors: Peter Huber, Winfried Kamp, Joel Hatsch, Michel d'Argouges, Siegmar Koeppe, Thomas Kuenemund
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Patent number: 8780648Abstract: A method of testing a latch based memory device is disclosed. The latch based memory device includes a number of latches, electrical connections and a circuit environment of the latches. A storage functionality of the latches can be tested during a first test phase while a functionality of the electrical connections and the circuit environment of the latches can be tested during a second test phase.Type: GrantFiled: November 21, 2012Date of Patent: July 15, 2014Assignee: Infineon Technologies AGInventors: Siegmar Koeppe, Winfried Kamp, Julie Aunis
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Patent number: 8605526Abstract: Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a “1” or “0” under normal read/write conditions, aspects of the present discloser relate to BIST tests that test the read and/or write margins of a cell. During this BIST testing, the read and/or write margins can be incrementally stressed until a failure point is determined for the cell. In this way, “weak” memory cells in an array can be identified and appropriate action can be taken, if necessary, to deal with these weak cells.Type: GrantFiled: May 31, 2011Date of Patent: December 10, 2013Assignee: Infineon Technologies AGInventors: Peter Huber, Joel Hatsch, Karl Hofmann, Siegmar Koeppe
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Patent number: 8331163Abstract: A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach.Type: GrantFiled: September 7, 2010Date of Patent: December 11, 2012Assignee: Infineon Technologies AGInventors: Siegmar Koeppe, Winfried Kamp, Julie Aunis
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Publication number: 20120307579Abstract: Some embodiments of the present disclosure relate to improved reliability verification techniques for semiconductor memories. Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a “1” or “0” under normal read/write conditions, aspects of the present invention relate to BIST tests that test the read and/or write margins of a cell. During this BIST testing, the read and/or write margins can be incrementally stressed until a failure point is determined for the cell. In this way, “weak” memory cells in an array can be identified and appropriate action can be taken, if necessary, to deal with these weak cells.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: Infineon Technologies AGInventors: Peter Huber, Joel Hatsch, Karl Hofmann, Siegmar Koeppe
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Patent number: 8243555Abstract: Implementations are presented herein that include a time delay path.Type: GrantFiled: August 7, 2008Date of Patent: August 14, 2012Assignee: Infineon Technologies AGInventors: Stephan Henzler, Siegmar Koeppe
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Patent number: 8223573Abstract: Method and device for controlling a memory access and correspondingly configured semiconductor memory A method and a device for controlling a memory access of a memory comprising memory cells are described. A completion of the memory access is determined by means of at least one dummy bit line. The at least one dummy bit line is connected to a plurality of memory cells of the memory cells of the memory such that a content of the at least one memory cell can be read out via the at least one dummy bit line. The at least one memory cell can be set to a predetermined potential. Each of said plurality of memory cells is connected to the at least one dummy bit line and to at least one dummy word line such that each of said plurality of memory cells can be set to the predetermined potential by means of the at least one dummy bit line and by means of the at least one dummy word line.Type: GrantFiled: February 26, 2009Date of Patent: July 17, 2012Assignee: Infineon Technologies AGInventors: Siegmar Koeppe, Martin Ostermayr
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Patent number: 8209523Abstract: A data moving processor includes a code memory coupled to a code fetch circuit and a decode circuit coupled to the code fetch circuit. An address stack is coupled to the decode circuit and configured to store address data. A general purpose stack is coupled to the decode circuit and configured to store other data. The data moving processor uses data from the general purpose stack to perform calculations. The data moving processor uses address data from the address stack to identify source and destination memory locations. The address data may be used to drive an address line of a memory during a read or write operation. The address stack and general purpose stack are separately controlled using bytecode.Type: GrantFiled: January 22, 2009Date of Patent: June 26, 2012Assignee: Intel Mobile Communications GmbHInventors: Ulf Nordqvist, Jinan Lin, Xiaoning Nie, Stefan Maier, Siegmar Koeppe
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Patent number: 8188780Abstract: A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.Type: GrantFiled: December 29, 2006Date of Patent: May 29, 2012Assignee: Infineon Technologies AGInventors: Christian Pacha, Siegmar Köppe, Karl Zapf
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Publication number: 20120057411Abstract: A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach.Type: ApplicationFiled: September 7, 2010Publication date: March 8, 2012Inventors: Siegmar Koeppe, Winfried Kamp, Julie Aunis
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Publication number: 20120020145Abstract: A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.Type: ApplicationFiled: June 17, 2011Publication date: January 26, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: Peter Huber, Winfried Kamp, Joel Hatsch, Michel d'Argouges, Siegmar Koeppe
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Publication number: 20100308863Abstract: An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.Type: ApplicationFiled: May 14, 2010Publication date: December 9, 2010Inventors: Jörg Gliese, Winfried Kamp, Siegmar Köppe, Michael Scheppler
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Patent number: 7755110Abstract: An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.Type: GrantFiled: March 24, 2005Date of Patent: July 13, 2010Assignee: Infineon Technologies AGInventors: Jörg Gliese, Winfried Kamp, Siegmar Köppe, Michael Scheppler
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Patent number: 7696829Abstract: A synthesizer arrangement includes an oscillator, a phase detector, and a loop filter that form a phase-locked loop. The loop filter is coupled to a control unit to activate a respective set of internal states out of a plurality of sets of internal states.Type: GrantFiled: September 21, 2006Date of Patent: April 13, 2010Assignee: Infineon Technologies AGInventors: Stephan Henzler, Siegmar Köppe
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Patent number: 7688126Abstract: A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.Type: GrantFiled: January 29, 2009Date of Patent: March 30, 2010Assignee: Infineon Technologies AGInventors: Stephan Henzler, Siegmar Köppe, Dominik Lorenz
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Publication number: 20100034056Abstract: Implementations are presented herein that include a time delay path.Type: ApplicationFiled: August 7, 2008Publication date: February 11, 2010Applicant: INFINEON TECHNOLOGIES AGInventors: Stephan HENZLER, Siegmar KOEPPE
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Patent number: 7656204Abstract: A divider circuit comprises at least two clock edge controlled differential buffer store elements, each being clocked by complementary input clock signals, each comprising internal storage nodes which are pre-chargeable to a pre-charge potential, and each comprising a differential data input. The internal storage nodes of the buffer store elements are either pre-charged at the pre-charge potential or store a logic level, depending on the relevant input clock signals. The differential data inputs of one of the buffer store elements is connected to the internal storage nodes of the other buffer store element and pulsed signals can be tapped off at the internal differential storage node.Type: GrantFiled: March 2, 2007Date of Patent: February 2, 2010Assignee: Infineon Technologies AGInventors: Stephan Henzler, Siegmar Koeppe
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Publication number: 20090213674Abstract: Method and device for controlling a memory access and correspondingly configured semiconductor memory A method and a device for controlling a memory access of a memory comprising memory cells are described. A completion of the memory access is determined by means of at least one dummy bit line. The at least one dummy bit line is connected to a plurality of memory cells of the memory cells of the memory such that a content of the at least one memory cell can be read out via the at least one dummy bit line. The at least one memory cell can be set to a predetermined potential. Each of said plurality of memory cells is connected to the at least one dummy bit line and to at least one dummy word line such that each of said plurality of memory cells can be set to the predetermined potential by means of the at least one dummy bit line and by means of the at least one dummy word line.Type: ApplicationFiled: February 26, 2009Publication date: August 27, 2009Applicant: INFINEON TECHNOLOGIES AGInventors: Siegmar Koeppe, Martin Ostermayr
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Patent number: 7564284Abstract: A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.Type: GrantFiled: March 26, 2007Date of Patent: July 21, 2009Assignee: Infineon Technologies AGInventors: Stephan Henzler, Siegmar Köppe, Dominik Lorenz
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Patent number: 7509561Abstract: A parity checking circuit is designed for continuous parity checking of content-addressable memory cells, and is configured such that during a parity check the number of parity checking steps per data word is the same as the number of bits in the original payload data word to be stored, with the parity checking circuit being formed from four transistors of the same conductance type. The parity checking circuit has a detector, which automatically detects the change in an information state of a memory cell. The detector is in the form of an automatic state device and has a number of catch latches.Type: GrantFiled: February 23, 2005Date of Patent: March 24, 2009Assignee: Infineon Technologies AGInventors: Winfried Kamp, Siegmar Köppe