Patents by Inventor Simon J. Lovett

Simon J. Lovett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210319825
    Abstract: Methods, systems, and devices for power-efficient generation of voltage are described. A driver circuit in a memory device may produce a voltage on an output node for other components in the memory device to use. To produce the voltage, the driver circuit may use a first voltage supply to charge the output node to a first threshold voltage level. The driver may then use a second voltage source to charge the output node to a second threshold voltage level that is different than (e.g., higher than) the first threshold voltage level.
    Type: Application
    Filed: April 27, 2021
    Publication date: October 14, 2021
    Inventor: Simon J. Lovett
  • Patent number: 11087835
    Abstract: Latch circuitry configured to latch data for use in the memory device. The latch circuitry includes latch cells each configured to store a bit of the data. The latch circuitry also includes a data line coupled to a first side of the latch cells and a data false line coupled to a second side of the latch cells. The latch circuitry also includes a write driver that includes an input configured to receive the data to be stored in the latch cells and a pair of inverters coupled to the input and configured to output a data signal to a first side of the latch cells. The latch circuitry also includes an inverter coupled to the input and configured to generate a data false signal to a second side of the latch cells. The data used to generate the data false signal is not passed through the pair of inverters.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hiroshi Akamatsu, Simon J. Lovett
  • Publication number: 20210142862
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
    Type: Application
    Filed: November 17, 2020
    Publication date: May 13, 2021
    Inventors: Simon J. Lovett, Richard E. Fackenthal
  • Patent number: 10998035
    Abstract: Methods, systems, and devices for power-efficient generation of voltage are described. A driver circuit in a memory device may produce a voltage on an output node for other components in the memory device to use. To produce the voltage, the driver circuit may use a first voltage supply to charge the output node to a first threshold voltage level. The driver may then use a second voltage source to charge the output node to a second threshold voltage level that is different than (e.g., higher than) the first threshold voltage level.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Simon J. Lovett
  • Publication number: 20210118482
    Abstract: Methods, systems, and devices for power-efficient generation of voltage are described. A driver circuit in a memory device may produce a voltage on an output node for other components in the memory device to use. To produce the voltage, the driver circuit may use a first voltage supply to charge the output node to a first threshold voltage level. The driver may then use a second voltage source to charge the output node to a second threshold voltage level that is different than (e.g., higher than) the first threshold voltage level.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Inventor: Simon J. Lovett
  • Patent number: 10957365
    Abstract: A semiconductor device may include a local power domain configured to selectively provide or prevent power to a logic block of the memory device and a temperature sensor located on the semiconductor device. The semiconductor device may also include timeout circuitry to delay a power down of the local power domain by a timeout time based at least in part on temperature information from the temperature sensor.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Simon J. Lovett
  • Publication number: 20210065786
    Abstract: Latch circuitry configured to latch data for use in the memory device. The latch circuitry includes latch cells each configured to store a bit of the data. The latch circuitry also includes a data line coupled to a first side of the latch cells and a data false line coupled to a second side of the latch cells. The latch circuitry also includes a write driver that includes an input configured to receive the data to be stored in the latch cells and a pair of inverters coupled to the input and configured to output a data signal to a first side of the latch cells. The latch circuitry also includes an inverter coupled to the input and configured to generate a data false signal to a second side of the latch cells. The data used to generate the data false signal is not passed through the pair of inverters.
    Type: Application
    Filed: July 13, 2020
    Publication date: March 4, 2021
    Inventors: Hiroshi Akamatsu, Simon J. Lovett
  • Patent number: 10861579
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Simon J. Lovett, Richard E. Fackenthal
  • Patent number: 10734067
    Abstract: Latch circuitry configured to latch data for use in the memory device. The latch circuitry includes latch cells each configured to store a bit of the data. The latch circuitry also includes a data line coupled to a first side of the latch cells and a data false line coupled to a second side of the latch cells. The latch circuitry also includes a write driver that includes an input configured to receive the data to be stored in the latch cells and a pair of inverters coupled to the input and configured to output a data signal to a first side of the latch cells. The latch circuitry also includes an inverter coupled to the input and configured to generate a data false signal to a second side of the latch cells. The data used to generate the data false signal is not passed through the pair of inverters.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hiroshi Akamatsu, Simon J. Lovett
  • Publication number: 20200075063
    Abstract: A semiconductor device may include a local power domain configured to selectively provide or prevent power to a logic block of the memory device and a temperature sensor located on the semiconductor device. The semiconductor device may also include timeout circuitry to delay a power down of the local power domain by a timeout time based at least in part on temperature information from the temperature sensor.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 5, 2020
    Inventor: Simon J. Lovett
  • Publication number: 20200013478
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
    Type: Application
    Filed: July 16, 2019
    Publication date: January 9, 2020
    Inventors: Simon J. Lovett, Richard E. Fackenthal
  • Patent number: 10522235
    Abstract: Various embodiments, disclosed herein, include apparatus and methods of using the apparatus having a core array of memory cells arranged as data storage elements; and an array of latches to store repair information for the core array. Each latch can be structured as a static random access memory cell. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: December 31, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Simon J. Lovett
  • Patent number: 10403389
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Simon J. Lovett, Richard E. Fackenthal
  • Publication number: 20190253050
    Abstract: Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds, at least in part, to a first change from a first state to a second state of a control signal to initiate supplying a power supply voltage from the power supply line to the internal circuit, and continue supplying the power supply voltage from the power supply line to internal circuit for at least a timeout period from a second change from the second state to the first state of the control signal, in which the timeout period represent temperature dependency.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Applicant: Micron Technology, Inc.
    Inventor: Simon J. Lovett
  • Patent number: 10305471
    Abstract: Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds, at least in part, to a first change from a first state to a second state of a control signal to initiate supplying a power supply voltage from the power supply line to the internal circuit, and continue supplying the power supply voltage from the power supply line to internal circuit for at least a timeout period from a second change from the second state to the first state of the control signal, in which the timeout period represent temperature dependency.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Simon J. Lovett
  • Publication number: 20190066819
    Abstract: Various embodiments, disclosed herein, include apparatus and methods of using the apparatus having a core array of memory cells arranged as data storage elements; and an array of latches to store repair information for the core array. Each latch can be structured as a static random access memory cell. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 28, 2019
    Inventor: Simon J. Lovett
  • Publication number: 20180286494
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Inventors: Simon J. Lovett, Richard E. Fackenthal
  • Publication number: 20180062640
    Abstract: Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds, at least in part, to a first change from a first state to a second state of a control signal to initiate supplying a power supply voltage from the power supply line to the internal circuit, and continue supplying the power supply voltage from the power supply line to internal circuit for at least a timeout period from a second change from the second state to the first state of the control signal, in which the timeout period represent temperature dependency.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 1, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: SIMON J. LOVETT
  • Patent number: 9772969
    Abstract: A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: September 26, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Simon J. Lovett
  • Patent number: 9508409
    Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: November 29, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Mark K. Hadrick, Jeffrey P. Wright, Victor Wong, Simon J. Lovett, Donald M. Morgan, William F. Jones, Sujeet Ayyapureddi, Dean D. Gans, Jongtae Kwak