Patents by Inventor Sinjeet Dhanvantray PAREKH
Sinjeet Dhanvantray PAREKH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10868550Abstract: A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.Type: GrantFiled: February 4, 2020Date of Patent: December 15, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jayawardan Janardhanan, Christopher Andrew Schell, Sinjeet Dhanvantray Parekh
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Publication number: 20200321969Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.Type: ApplicationFiled: June 23, 2020Publication date: October 8, 2020Inventors: Jayawardan JANARDHANAN, Christopher Andrew SCHELL, Arvind SRIDHAR, Sinjeet Dhanvantray PAREKH
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Patent number: 10727846Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.Type: GrantFiled: September 25, 2019Date of Patent: July 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jayawardan Janardhanan, Christopher Andrew Schell, Arvind Sridhar, Sinjeet Dhanvantray Parekh
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Patent number: 10691074Abstract: A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.Type: GrantFiled: May 6, 2019Date of Patent: June 23, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry Yao, Sinjeet Dhanvantray Parekh
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Patent number: 10686456Abstract: A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.Type: GrantFiled: December 13, 2018Date of Patent: June 16, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jayawardan Janardhanan, Christopher Andrew Schell, Sinjeet Dhanvantray Parekh
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Publication number: 20200177192Abstract: A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.Type: ApplicationFiled: February 4, 2020Publication date: June 4, 2020Inventors: Jayawardan JANARDHANAN, Christopher Andrew SCHELL, Sinjeet Dhanvantray PAREKH
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Publication number: 20200021301Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.Type: ApplicationFiled: September 25, 2019Publication date: January 16, 2020Inventors: Jayawardan JANARDHANAN, Christopher Andrew SCHELL, Arvind SRIDHAR, Sinjeet Dhanvantray PAREKH
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Patent number: 10505555Abstract: A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.Type: GrantFiled: December 20, 2018Date of Patent: December 10, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sinjeet Dhanvantray Parekh, Jayawardan Janardhanan, Christopher Andrew Schell, Arvind Sridhar
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Patent number: 10498344Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.Type: GrantFiled: December 27, 2018Date of Patent: December 3, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jayawardan Janardhanan, Christopher Andrew Schell, Arvind Sridhar, Sinjeet Dhanvantray Parekh
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Patent number: 10496041Abstract: A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.Type: GrantFiled: May 29, 2018Date of Patent: December 3, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry Yao, Sinjeet Dhanvantray Parekh
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Patent number: 10491222Abstract: A phase-locked loop (PLL) includes a selection circuit including a plurality of inputs, each input to receive a separate reference clock. A programmable reference clock divider divides down the reference clock selected by the selection circuit to generate a divided down reference clock. A feedback clock divider divides down an output clock from the PLL to generate a feedback clock. A time-to-digital converter (TDC) generates a digital output value based on a phase difference between the divided down reference clock and the feedback clock. A circuit including a finite state machine, causes, responsive to an indication to change reference clocks, the reference clock divider and the feedback clock divider to be held in a reset state, the divide ratio of the reference clock divider to be modified, and then to release the reset state.Type: GrantFiled: December 20, 2018Date of Patent: November 26, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sinjeet Dhanvantray Parekh, Eric Paul Lindgren, Christopher Andrew Schell, Jayawardan Janardhanan
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Publication number: 20190339651Abstract: A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.Type: ApplicationFiled: May 6, 2019Publication date: November 7, 2019Inventors: Henry YAO, Sinjeet Dhanvantray PAREKH
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Publication number: 20190339650Abstract: A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.Type: ApplicationFiled: May 29, 2018Publication date: November 7, 2019Inventors: Henry YAO, Sinjeet Dhanvantray PAREKH
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Publication number: 20190288699Abstract: A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.Type: ApplicationFiled: December 20, 2018Publication date: September 19, 2019Inventors: Sinjeet Dhanvantray PAREKH, Jayawardan JANARDHANAN, Christopher Andrew SCHELL, Arvind SRIDHAR
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Publication number: 20190288695Abstract: A phase-locked loop (PLL) system includes a first PLL coupled to receive a first reference clock. The PLL system also includes a second PLL coupled to receive a second reference clock. The output of the second PLL is coupled to the first PLL, and the second PLL is configured to control the first PLL. The PLL system further includes a third PLL coupled to receive an input reference clock. The output of the third PLL is coupled to the second PLL. The third PLL is configured to control the second PLL.Type: ApplicationFiled: December 27, 2018Publication date: September 19, 2019Inventors: Henry YAO, Arvind SRIDHAR, Sinjeet Dhanvantray PAREKH, Jayawardan JANARDHANAN
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Publication number: 20190288694Abstract: A phase-locked loop (PLL) includes a selection circuit including a plurality of inputs, each input to receive a separate reference clock. A programmable reference clock divider divides down the reference clock selected by the selection circuit to generate a divided down reference clock. A feedback clock divider divides down an output clock from the PLL to generate a feedback clock. A time-to-digital converter (TDC) generates a digital output value based on a phase difference between the divided down reference clock and the feedback clock. A circuit including a finite state machine, causes, responsive to an indication to change reference clocks, the reference clock divider and the feedback clock divider to be held in a reset state, the divide ratio of the reference clock divider to be modified, and then to release the reset state.Type: ApplicationFiled: December 20, 2018Publication date: September 19, 2019Inventors: Sinjeet Dhanvantray PAREKH, Eric Paul LINDGREN, Christopher Andrew SCHELL, Jayawardan JANARDHANAN
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Publication number: 20190280699Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.Type: ApplicationFiled: December 27, 2018Publication date: September 12, 2019Inventors: Jayawardan JANARDHANAN, Christopher Andrew SCHELL, Arvind SRIDHAR, Sinjeet Dhanvantray PAREKH
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Publication number: 20190280700Abstract: A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.Type: ApplicationFiled: December 13, 2018Publication date: September 12, 2019Inventors: Jayawardan JANARDHANAN, Christopher Andrew SCHELL, Sinjeet Dhanvantray PAREKH