Abstract: Disclosed is a scanning interference photolithography system, comprising a heterodyne optical path, a first interference optical path, a second interference optical path, a motion platform and a control subsystem, wherein a substrate is carried on the motion platform, a displacement measurement interferometer is used to measure the displacement of the motion platform, a first light beam and a second light beam are focused on the substrate for interference exposure; the control subsystem generates instructions according to various measurement information, adjusts angles of corresponding devices or the phase of a light beam, and locks the phase shift of interference exposure fringes of the first light beam and the second light beam. The system has a high precision of fringe pattern locking and a high laser utilization rate, and can be used for producing a large-area high-precision dense grating line gradient periodic grating.

Abstract: The disclosure provides an array substrate, a display panel and a displaying device, relating to the technical field of display ambient light. The array substrate has an active area and a peripheral area located on at least one side of the active area. The array substrate comprises a brightness detection module and a reference module. The brightness detection module is arranged in the peripheral area, comprising at least one first thin-film transistor. The brightness detection module is configured to receive ambient light, generate an ambient light brightness detecting current signal in response to the ambient light and output the ambient light brightness detecting current signal. The reference module is arranged in the peripheral area, comprising at least one second thin-film transistor. The reference module is configured to, in a dark state without ambient light, generate and output a reference current signal.

Abstract: An Electro-Static Discharge (ESD) protection circuit is disclosed. In some implementations, the ESD protection circuit includes a first ESD diode, a second ESD diode, a passive equalization network and a programmable resistor network. The first ESD diode is coupled to the passive equalization network. The programmable resistor network is coupled between the passive equalization network and the second ESD diode. The programmable resistor network can be programmed to place the ESD protection circuit in one of a plurality of receiver modes based on a type of a transmitter from which the receiver is receiving signals.

Abstract: Aspects of the disclosure are directed to a low noise T-coil design. In accordance with one aspect, an input/output (I/O) circuit includes a first T-coil, wherein the first T-coil includes a first set of two inductors connected to each other in series arranged to accommodate a first current flow to produce a first magnetic field with a first perpendicular direction; and a second T-coil, wherein the second T-coil includes a second set of two inductors connected to each other in series arranged to accommodate a second current flow to produce a second magnetic field with a second perpendicular direction; and wherein the second magnetic field cancels the first magnetic field.

Abstract: A T-coil IC includes a first inductor on an Mx layer. The first inductor has n turns, where n is at least 1? turns. The T-coil IC further includes a second inductor on an Mx?1 layer. The second inductor has n turns. The first inductor and the second inductor are connected together at a node. The first inductor on the Mx layer and the second inductor on the Mx?1 layer are mirror symmetric to each other. The T-coil IC further includes a center tap on an Mx?2?y layer, where y?0. The center tap is connected to the first inductor and the second inductor by a via stack at the node. In one configuration, n is 1?+0.5z turns, where z?0. An effective bridge capacitance of the T-coil IC may be approximately 25 fF.

Abstract: For a T-coil IC, a first inductor core is on an Mx layer, has at least 1? turns, and has a first-inductor-core-first end and a first-inductor-core-second end. A second inductor core is on an Mx-1 layer, has at least 2? turns, and has a second-inductor-core-first end and a second-inductor-core-second end. The first-inductor-core-second end is connected to the second-inductor-core-first end at a node. A third inductor core is on an Mx-2 layer and has at least 3 turns. The third inductor core has a third-inductor-core-first end and a third-inductor-core-second end. The second-inductor-core-second end is connected to the third-inductor-core-first end. A tap is on an Mx-3-y layer, where y?0. The tap is connected to the first and second inductor cores at the node. A first inductor is formed by the first inductor core, and a second inductor is formed by the second and third inductor cores.

Abstract: For a T-coil IC, a first inductor core is on an Mx layer and has n turns (n?15/8). The first inductor core has a first-inductor-core-first end and a first-inductor-core-second end. A second inductor core is on an Mx-2 layer and has n turns. The second inductor core has a second-inductor-core-first end and a second-inductor-core-second end. The first-inductor-core-second end is connected to the second-inductor-core-first end by a via stack between the Mx and Mx-2 layers. A center tap is on an Mx-1 layer. The center tap is connected to the second inductor core at a node of the second inductor core. A first inductor is formed by the first inductor core between the first-inductor-core-first end and the first-inductor-core-second end and by the second inductor core between the second-inductor-core-first end and the node. A second inductor is formed by the second inductor core between the node and the second-inductor-core-second end.

Abstract: An Electro-Static Discharge (ESD) protection circuit is disclosed. In some implementations, the ESD protection circuit includes a first ESD diode, a second ESD diode, a passive equalization network and a programmable resistor network. The first ESD diode is coupled to the passive equalization network. The programmable resistor network is coupled between the passive equalization network and the second ESD diode. The programmable resistor network can be programmed to place the ESD protection circuit in one of a plurality of receiver modes based on a type of a transmitter from which the receiver is receiving signals.

Abstract: A T-coil IC includes a first inductor on an Mx layer. The first inductor has n turns, where n is at least 1? turns. The T-coil IC further includes a second inductor on an Mx-1 layer. The second inductor has n turns. The first inductor and the second inductor are connected together at a node. The first inductor on the Mx layer and the second inductor on the Mx-1 layer are mirror symmetric to each other. The T-coil IC further includes a center tap on an Mx-2-y layer, where y?0. The center tap is connected to the first inductor and the second inductor by a via stack at the node. In one configuration, n is 1?+0.5z turns, where z?0. An effective bridge capacitance of the T-coil IC may be approximately 25 fF.

Abstract: For a T-coil IC, a first inductor core is on an Mx layer, has at least 1? turns, and has a first-inductor-core-first end and a first-inductor-core-second end. A second inductor core is on an Mx-1 layer, has at least 2? turns, and has a second-inductor-core-first end and a second-inductor-core-second end. The first-inductor-core-second end is connected to the second-inductor-core-first end at a node. A third inductor core is on an Mx-2 layer and has at least 3 turns. The third inductor core has a third-inductor-core-first end and a third-inductor-core-second end. The second-inductor-core-second end is connected to the third-inductor-core-first end. A tap is on an Mx-3-y layer, where y>0. The tap is connected to the first and second inductor cores at the node. A first inductor is formed by the first inductor core, and a second inductor is formed by the second and third inductor cores.

Abstract: For a T-coil IC, a first inductor core is on an Mx layer and has n turns (n?15/8). The first inductor core has a first-inductor-core-first end and a first-inductor-core-second end. A second inductor core is on an Mx-2 layer and has n turns. The second inductor core has a second-inductor-core-first end and a second-inductor-core-second end. The first-inductor-core-second end is connected to the second-inductor-core-first end by a via stack between the Mx and Mx-2 layers. A center tap is on an Mx-1 layer. The center tap is connected to the second inductor core at a node of the second inductor core. A first inductor is formed by the first inductor core between the first-inductor-core-first end and the first-inductor-core-second end and by the second inductor core between the second-inductor-core-first end and the node. A second inductor is formed by the second inductor core between the node and the second-inductor-core-second end.

Abstract: An integrated circuit (IC) inductor structure is provided with transverse electrical interfaces. The inductor structure is formed on at least one IC circuit layer and has a first axis planar to a circuit layer surface, bisecting the inductor into opposite first and second sides. An input interface is formed on the circuit layer and connected to the inductor first side, parallel to a second axis, which is perpendicular to the first axis. An output interface is formed on the circuit layer and connected to the inductor second side, parallel to the second axis. In one aspect, the inductor has a center tap electrical interface parallel to the axis. In another aspect, the inductor includes a three-dimensional (3D) loop formed over a plurality of the circuit layers.

Abstract: An integrated circuit (IC) inductor structure is provided with transverse electrical interfaces. The inductor structure is formed on at least one IC circuit layer and has a first axis planar to a circuit layer surface, bisecting the inductor into opposite first and second sides. An input interface is formed on the circuit layer and connected to the inductor first side, parallel to a second axis, which is perpendicular to the first axis. An output interface is formed on the circuit layer and connected to the inductor second side, parallel to the second axis. In one aspect, the inductor has a center tap electrical interface parallel to the axis. In another aspect, the inductor includes a three-dimensional (3D) loop formed over a plurality of the circuit layers.

Abstract: An integrated circuit (IC) multilevel inductor structure is provided. The IC multilayer inductor structure is made from an IC including a plurality of circuit layers, where the inductor is a three-dimensional (3D) loop formed over a plurality of the circuit layers. In a simple example, if the IC includes a first circuit layer and a second circuit layer, then the inductor 3D loop includes a first partial loop portion formed on the first circuit layer, a second partial loop portion formed on the second circuit layer, and a via connecting the first and second partial loop portions. More generally, the inductor typically includes a plurality of 3D loops. A first plurality of 3D loops is formed between the input and an nth circuit layer, and a second plurality of 3D loops is formed between the nth circuit layer and the output.

Abstract: A modeling system for active semiconductor devices, such as gallium arsenide field effect transistors, for nonlinear (e.g., harmonic balance) circuit simulation. The model enables fast and unambiguous construction (model generation) by explicit calculations applied to raw device response data obtained using an adaptive, automated data acquisition system employed to characterize the device. The automated data acquisition system obtains the data adaptively, taking more data where nonlinearities are most severe and within a calculated, safe operating range of the device. The system converts conventional d.c. and S-parameter data directly into a detailed, device-specific, large-signal model. The system is extremely fast and replaces the need for conventional parameter extraction based on circuit simulation and optimization techniques.