Patents by Inventor SIVA SOUMYA EACHEMPATI

SIVA SOUMYA EACHEMPATI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiple dies hardware processors and methods
    Patent number: 11899615
    Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
    Type: Grant
    Filed: January 27, 2023
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z Chrysos, John R. Ayers, Dheeraj R. Subbareddy
  • MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
    Publication number: 20230169032
    Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
    Type: Application
    Filed: January 27, 2023
    Publication date: June 1, 2023
    Inventors: NEVINE NASSIF, YEN-CHENG LIU, KRISHNAKANTH V. SISTLA, GERALD PASDAST, SIVA SOUMYA EACHEMPATI, TEJPAL SINGH, ANKUSH VARMA, MAHESH K. KUMASHIKAR, SRIKANTH NIMMAGADDA, CARLETON L. MOLNAR, VEDARAMAN GEETHA, JEFFREY D. CHAMBERLAIN, WILLIAM R. HALLECK, GEORGE Z. CHRYSOS, JOHN R. AYERS, DHEERAJ R. SUBBAREDDY
  • Multiple dies hardware processors and methods
    Patent number: 11586579
    Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: February 21, 2023
    Assignee: Intel Corporation
    Inventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z. Chrysos, John R. Ayers, Dheeraj R. Subbareddy
  • Multiple dies hardware processors and methods
    Patent number: 11294852
    Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z. Chrysos, John R. Ayers, Dheeraj R. Subbareddy
  • MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
    Publication number: 20220050805
    Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
    Type: Application
    Filed: October 28, 2021
    Publication date: February 17, 2022
    Inventors: NEVINE NASSIF, YEN-CHENG LIU, KRISHNAKANTH V. SISTLA, GERALD PASDAST, SIVA SOUMYA EACHEMPATI, TEJPAL SINGH, ANKUSH VARMA, MAHESH K. KUMASHIKAR, SRIKANTH NIMMAGADDA, CARLETON L. MOLNAR, VEDARAMAN GEETHA, JEFFREY D. CHAMBERLAIN, WILLIAM R. HALLECK, GEORGE Z. CHRYSOS, JOHN R. AYERS, DHEERAJ R. SUBBAREDDY
  • MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
    Publication number: 20200334196
    Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Inventors: NEVINE NASSIF, YEN-CHENG LIU, KRISHNAKANTH V. SISTLA, GERALD PASDAST, SIVA SOUMYA EACHEMPATI, TEJPAL SINGH, ANKUSH VARMA, MAHESH K. KUMASHIKAR, SRIKANTH NIMMAGADDA, CARLETON L. MOLNAR, VEDARAMAN GEETHA, JEFFREY D. CHAMBERLAIN, WILLIAM R. HALLECK, GEORGE Z. CHRYSOS, JOHN R. AYERS, DHEERAJ R. SUBBAREDDY
  • Multiple dies hardware processors and methods
    Patent number: 10795853
    Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z. Chrysos, John R. Ayers, Dheeraj R. Subbareddy
  • MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
    Publication number: 20180101502
    Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
    Type: Application
    Filed: September 30, 2017
    Publication date: April 12, 2018
    Inventors: NEVINE NASSIF, YEN-CHENG LIU, KRISHNAKANTH V. SISTLA, GERALD PASDAST, SIVA SOUMYA EACHEMPATI, TEJPAL SINGH, ANKUSH VARMA, MAHESH K. KUMASHIKAR, SRIKANTH NIMMAGADDA, CARLETON L. MOLNAR, VEDARAMAN GEETHA, JEFFREY D. CHAMBERLAIN, WILLIAM R. HALLECK, GEORGE Z. CHRYSOS, JOHN R. AYERS, DHEERAJ R. SUBBAREDDY