Patents by Inventor Skyler Jonathon Saleh

Skyler Jonathon Saleh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11393156
    Abstract: Techniques for performing ray tracing for a ray are provided. The techniques include, based on first traversal of a bounding volume hierarchy, identifying a first memory page that is classified as resident, obtaining a first portion of the bounding volume hierarchy associated with the first memory page, traversing the first portion of the bounding volume hierarchy according to a ray intersection test, based on second traversal of the bounding volume hierarchy, identifying a second memory page that is classified as valid and non-resident, and in response to the second memory page being classified as valid and non-resident, determining that a miss occurs for each node of the bounding volume hierarchy within the second memory page.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: July 19, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Fataneh Ghodrat
  • Patent number: 11393157
    Abstract: A technique for classifying a ray tracing intersection with a triangle edge or vertex avoids either rendering holes or multiple hits of the same ray for different triangles. The technique employs a tie-breaking scheme in which certain types of edges are classified as hits and certain types of edges are classified as misses. The test is performed in a coordinate space that comprises a projection into the viewspace of the ray, and thus where the ray direction has a non-zero magnitude in one axis (e.g., z) but a zero magnitude in the two other axes. In this coordinate space, edges are classified as one of top, bottom, left, and right, and an intersection on an edge counts as a hit if the intersection hits a top or left edge, but a miss if the intersection hits a bottom or right edge. Vertices are processed in a related manner.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: July 19, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Skyler Jonathon Saleh
  • Publication number: 20220198739
    Abstract: A technique for performing ray tracing operations is provided. The technique includes performing bounding volume hierarchy (“BVH”) traversal in multiple accelerated processing devices (“APDs”), utilizing bounding volume hierarchy data copies in memories local to the multiple APDs; rendering primitives determined to be intersected based on the BVH traversal, using geometry information and texture data spread across the memories local to the multiple APDs; and storing results of rendered primitives for a set of tiles assigned to the multiple APDs into tile buffers stored in APD memories local to the APDs.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Maxim V. Kazakov, Swapnil P. Sakharshete, Takahiro Harada, Vineet Goel
  • Publication number: 20220189096
    Abstract: Techniques for performing ray tracing operations are provided. The techniques include dividing a primitive of a scene to generate primitive portions; identifying, from the primitive portions, and based on an opacity texture, one or more opaque primitive portions and one or more invisible primitive portions; generating box nodes for a bounding volume hierarchy corresponding to the opaque primitive portions, but not the invisible primitive portions; and inserting the generated box nodes into the bounding volume hierarchy.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 16, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Ruijin Wu, Sagar S. Bhandare, Young In Yeo, Skyler Jonathon Saleh
  • Patent number: 11321903
    Abstract: A technique for performing ray tracing operations is provided. The technique includes receiving a ray for an intersection test, testing the ray against boxes specified in a bounding volume hierarchy to eliminate one or more boxes or triangles from consideration, unpacking a triangle from a compressed triangle block of the bounding volume hierarchy, the compressed triangle block including two or more triangles that share at least one vertex, and testing the ray for intersection against at least one of the unpacked triangles.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 3, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Young In Yeo
  • Patent number: 11276223
    Abstract: Described herein is a merged data path unit that has elements that are configurable to switch between different instruction types. The merged data path unit is a pipelined unit that has multiple stages. Between different stages lie multiplexor layers that are configurable to route data from functional blocks of a prior stage to a subsequent stage. The manner in which the multiplexor layers are configured for a particular stage is based on the instruction type executed at that stage. In some implementations, the functional blocks in different stages are also configurable by the control unit to change the operations performed. Further, in some implementations, the control unit has sideband storage that stores data that “skips stages.” An example of a merged data path used for performing a ray-triangle intersection test and a ray-box intersection test is also described herein.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 15, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Jian Mao
  • Patent number: 11276211
    Abstract: A technique for performing rasterization and pixel shading with decoupled resolution is provided herein. The technique involves performing rasterization as normal to generate quads. The quads are accumulated into a tile buffer. A shading rate is determined for the contents of the tile buffer. If the shading rate is a sub-sampling shading rate, then the quads in the tile buffer are down-sampled, which reduces the amount of work to be performed by a pixel shader. The shaded down-sampled quads are then restored to the resolution of the render target. If the shading rate is a super-sampling shading rate, then the quads in the tile buffer are up-sampled. The results of the shaded down-sampled or up-sampled quads are written to the render target.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 15, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Andrew S. Pomianowski
  • Patent number: 11257273
    Abstract: Techniques for processing pixel data are provided. The techniques include, in a first mode in which blending is enabled, reading in render target color data from a memory system; blending the render target color data with one or more fragments received from a pixel shader stage to generate blended color data; outputting the blended color data to the memory system utilizing a first amount of bandwidth; in a second mode in which blending is disabled and variable rate shading is enabled, amplifying shaded coarse fragments received from the pixel shader stage to generate fine fragments; and outputting the fine fragments to the memory system utilizing a second amount of bandwidth that is higher than the first amount of bandwidth.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: February 22, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pazhani Pillai, Skyler Jonathon Saleh
  • Patent number: 11238640
    Abstract: A technique for performing ray tracing operations is provided. The technique includes reading descendant-shared type metadata for a non-leaf node of a bounding volume hierarchy; identifying one or more culling types for a ray-intersection test for a ray; and determining whether to treat the non-leaf node as not intersected based on whether the one or more culling types includes at least one type specified by the descendant-shared type metadata.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: February 1, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Sagar S. Bhandare, Fataneh F. Ghodrat, Paul Raymond Vella
  • Publication number: 20220012933
    Abstract: Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, and updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data.
    Type: Application
    Filed: September 23, 2021
    Publication date: January 13, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Vineet Goel, Pazhani Pillai, Ruijin Wu, Christopher J. Brennan, Andrew S. Pomianowski
  • Patent number: 11222397
    Abstract: This disclosure describes examples for foveation rendering. A graphics processing unit (GPU) may render image content for each tile at different sizes as part of the rendering pass after a binning pass in which the GPU determined to which tiles vertices of primitives belong. The GPU may upsample the rendered image content based on the size at which GPU rendered the image content, and output the upsampled image content for later display.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 11, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Skyler Jonathon Saleh, David Rigel Garcia Garcia, Maurice Franklin Ribble
  • Publication number: 20210407175
    Abstract: A technique for performing ray tracing operations is provided. The technique includes reading descendant-shared type metadata for a non-leaf node of a bounding volume hierarchy; identifying one or more culling types for a ray-intersection test for a ray; and determining whether to treat the non-leaf node as not intersected based on whether the one or more culling types includes at least one type specified by the descendant-shared type metadata.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 30, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Sagar S. Bhandare, Fataneh F. Ghodrat, Paul Raymond Vella
  • Patent number: 11200724
    Abstract: A texture processor based ray tracing accelerator method and system are described. The system includes a shader, texture processor (TP) and cache, which are interconnected. The TP includes a texture address unit (TA), a texture cache processor (TCP), a filter pipeline unit and a ray intersection engine. The shader sends a texture instruction which contains ray data and a pointer to a bounded volume hierarchy (BVH) node to the TA. The TCP uses an address provided by the TA to fetch BVH node data from the cache. The ray intersection engine performs ray-BVH node type intersection testing using the ray data and the BVH node data. The intersection testing results and indications for BVH traversal are returned to the shader via a texture data return path. The shader reviews the intersection results and the indications to decide how to traverse to the next BVH node.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 14, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Maxim V. Kazakov, Vineet Goel
  • Publication number: 20210342996
    Abstract: A technique for performing a ray intersection test, the method comprising: receiving a request for an early termination ray intersection test for a ray; testing the ray against one or more early termination box nodes and one or more normal box nodes of a bounding volume hierarchy; and based on the test of the ray against the one or more early termination box nodes, determining whether to end traversal of the bounding volume hierarchy and determine whether the ray intersects geometry for the purpose of the ray intersection test.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 4, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Chen Huang
  • Patent number: 11158106
    Abstract: Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data, and writing a VRS rate feedback buffer based on the updated VRS data.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 26, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Vineet Goel, Pazhani Pillai, Ruijin Wu, Christopher J. Brennan, Andrew S. Pomianowski
  • Patent number: 11158112
    Abstract: Techniques for performing ray tracing operations are provided. The techniques include identifying bounding-box-surface-area-weighted centroid of a group of primitives associated with a bounding box of a bounding volume hierarchy (“BVH”); generating candidate splits at the centroid, the candidate splits defining geometry subgroups; identifying a candidate split having a lowest surface area bounding box; and generating nodes for the BVH that include geometry of the geometry subgroups of the identified candidate split.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: October 26, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Young In Yeo, Skyler Jonathon Saleh
  • Publication number: 20210304484
    Abstract: A technique for performing ray tracing operations is provided. The technique includes receiving a ray for an intersection test, testing the ray against boxes specified in a bounding volume hierarchy to eliminate one or more boxes or triangles from consideration, unpacking a triangle from a compressed triangle block of the bounding volume hierarchy, the compressed triangle block including two or more triangles that share at least one vertex, and testing the ray for intersection against at least one of the unpacked triangles.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Young In Yeo
  • Publication number: 20210304486
    Abstract: A technique for compressing an original image is disclosed. According to the technique, an original image is obtained and a delta-encoded image is generated based on the original image. Next, a segregated image is generated based on the delta-encoded image and then the segregated image is compressed to produce a compressed image. The segregated image is generated because the segregated image may be compressed more efficiently than the original image and the delta image.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ruijin Wu, Skyler Jonathon Saleh, Christopher J. Brennan, Kei Ming Kwong, Anthony Hung-Cheong Chan
  • Publication number: 20210287421
    Abstract: A technique for performing a ray tracing operation for a ray is provided. The method includes performing one or more ray-box intersection tests for the ray against one or more bounding boxes of a bounding volume hierarchy to eliminate one or more nodes of the bounding volume hierarchy from consideration, for one or more triangles of the bounding volume hierarchy that are not eliminated by the one or more ray-box intersection tests, performing one or more ray-triangle intersection tests utilizing samples displaced from a centroid position of the ray, and invoking one or more shaders of a ray tracing pipeline for the samples based on results of the ray-triangle intersection tests.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Chen Huang
  • Publication number: 20210287422
    Abstract: Techniques for performing ray tracing for a ray are provided. The techniques include, based on first traversal of a bounding volume hierarchy, identifying a first memory page that is classified as resident, obtaining a first portion of the bounding volume hierarchy associated with the first memory page, traversing the first portion of the bounding volume hierarchy according to a ray intersection test, based on second traversal of the bounding volume hierarchy, identifying a second memory page that is classified as valid and non-resident, and in response to the second memory page being classified as valid and non-resident, determining that a miss occurs for each node of the bounding volume hierarchy within the second memory page.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Fataneh Ghodrat