Patents by Inventor Skyler Jonathon Saleh

Skyler Jonathon Saleh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200302677
    Abstract: A technique for classifying a ray tracing intersection with a triangle edge or vertex avoids either rendering holes or multiple hits of the same ray for different triangles. The technique employs a tie-breaking scheme in which certain types of edges are classified as hits and certain types of edges are classified as misses. The test is performed in a coordinate space that comprises a projection into the viewspace of the ray, and thus where the ray direction has a non-zero magnitude in one axis (e.g., z) but a zero magnitude in the two other axes. In this coordinate space, edges are classified as one of top, bottom, left, and right, and an intersection on an edge counts as a hit if the intersection hits a top or left edge, but a miss if the intersection hits a bottom or right edge. Vertices are processed in a related manner.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Skyler Jonathon Saleh
  • Patent number: 10706609
    Abstract: Described herein is a technique for performing ray-triangle intersection without a floating point division unit. A division unit would be useful for a straightforward implementation of a certain type of ray-triangle intersection test that is useful in ray tracing operations. This certain type of ray-triangle intersection test includes a step that transforms the coordinate system into the viewspace of the ray, thereby reducing the problem of intersection to one of 2D triangle rasterization. However, a straightforward implementation of this transformation requires floating point division, as the transformation utilizes a shear operation to set the coordinate system such that the magnitudes of the ray direction on two of the axes are zero. Instead of using the most straightforward implementation of this transform, the technique described herein scales the entire coordinate system by the magnitude of the ray direction in the axis that is the denominator of the shear ratio, removing division.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: July 7, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Ruijin Wu
  • Publication number: 20200202605
    Abstract: A technique for determining the centroid for fragments generated using variable rate shading is provided. Because the barycentric interpolation used to determine texture coordinates for pixels is based on the premise that the point being interpolated is within the triangle, centroids that are outside of the triangle can produce undesirable visual artifacts. Another concern, however, is that the further the centroid is from the center of a pixel, the less accurate quad-based pixel derivatives become for attributes of that pixel. To address these concerns, the position of the sample that is both covered by the triangle and the closest to the center of the pixel, out of all covered samples of the pixel, is used as the centroid for a partially covered pixel. For a fully covered pixel (all samples in a pixel are covered by a triangle), the center of that pixel is used as the centroid.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Pazhani Pillai
  • Publication number: 20200202594
    Abstract: A technique for performing rasterization and pixel shading with decoupled resolution is provided herein. The technique involves performing rasterization as normal to generate quads. The quads are accumulated into a tile buffer. A shading rate is determined for the contents of the tile buffer. If the shading rate is a sub-sampling shading rate, then the quads in the tile buffer are down-sampled, which reduces the amount of work to be performed by a pixel shader. The shaded down-sampled quads are then restored to the resolution of the render target. If the shading rate is a super-sampling shading rate, then the quads in the tile buffer are up-sampled. The results of the shaded down-sampled or up-sampled quads are written to the render target.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Andrew S. Pomianowski
  • Patent number: 10692271
    Abstract: A technique for classifying a ray tracing intersection with a triangle edge or vertex avoids either rendering holes or multiple hits of the same ray for different triangles. The technique employs a tie-breaking scheme in which certain types of edges are classified as hits and certain types of edges are classified as misses. The test is performed in a coordinate space that comprises a projection into the viewspace of the ray, and thus where the ray direction has a non-zero magnitude in one axis (e.g., z) but a zero magnitude in the two other axes. In this coordinate space, edges are classified as one of top, bottom, left, and right, and an intersection on an edge counts as a hit if the intersection hits a top or left edge, but a miss if the intersection hits a bottom or right edge. Vertices are processed in a related manner.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 23, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Skyler Jonathon Saleh
  • Publication number: 20200193682
    Abstract: Described herein is a merged data path unit that has elements that are configurable to switch between different instruction types. The merged data path unit is a pipelined unit that has multiple stages. Between different stages lie multiplexor layers that are configurable to route data from functional blocks of a prior stage to a subsequent stage. The manner in which the multiplexor layers are configured for a particular stage is based on the instruction type executed at that stage. In some implementations, the functional blocks in different stages are also configurable by the control unit to change the operations performed. Further, in some implementations, the control unit has sideband storage that stores data that “skips stages.” An example of a merged data path used for performing a ray-triangle intersection test and a ray-box intersection test is also described herein.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Jian Mao
  • Publication number: 20200193683
    Abstract: A technique for classifying a ray tracing intersection with a triangle edge or vertex avoids either rendering holes or multiple hits of the same ray for different triangles. The technique employs a tie-breaking scheme in which certain types of edges are classified as hits and certain types of edges are classified as misses. The test is performed in a coordinate space that comprises a projection into the viewspace of the ray, and thus where the ray direction has a non-zero magnitude in one axis (e.g., z) but a zero magnitude in the two other axes. In this coordinate space, edges are classified as one of top, bottom, left, and right, and an intersection on an edge counts as a hit if the intersection hits a top or left edge, but a miss if the intersection hits a bottom or right edge. Vertices are processed in a related manner.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Skyler Jonathon Saleh
  • Publication number: 20200193673
    Abstract: A technique for executing pixel shader programs is provided. The pixel shader programs are executed in workgroups, which allows access by work-items to a local data store and also allows program synchronization at barrier points. Utilizing workgroups allows for more flexible and efficient execution than previous implementations in the pixel shader stage. Several techniques for assigning fragments to wavefronts and workgroups are also provided. The techniques differ in the degree of geometric locality of fragments within wavefronts and/or workgroups. In some techniques, a greater degree of locality is enforced, which reduces processing unit occupancy but also reduces program complexity. In other techniques, a lower degree of locality is enforced, which increases processing unit occupancy.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Skyler Jonathon Saleh
  • Publication number: 20200193684
    Abstract: Described herein is a technique for performing ray-triangle intersection without a floating point division unit. A division unit would be useful for a straightforward implementation of a certain type of ray-triangle intersection test that is useful in ray tracing operations. This certain type of ray-triangle intersection test includes a step that transforms the coordinate system into the viewspace of the ray, thereby reducing the problem of intersection to one of 2D triangle rasterization. However, a straightforward implementation of this transformation requires floating point division, as the transformation utilizes a shear operation to set the coordinate system such that the magnitudes of the ray direction on two of the axes are zero. Instead of using the most straightforward implementation of this transform, the technique described herein scales the entire coordinate system by the magnitude of the ray direction in the axis that is the denominator of the shear ratio, removing division.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Ruijin Wu
  • Publication number: 20200193681
    Abstract: Described herein is a technique for performing ray tracing. According to this technique, instead of executing intersection and/or any hit shaders during traversal of an acceleration structure to determine the closest hit for a ray, an acceleration structure is fully traversed in an invocation of a shader program, and the closest intersection with a triangle is recorded in a data structure associated with the material of the triangle. Later, a scheduler launches waves by grouping together multiple data items associated with the same material. The rays processed by that wave are processed with a continuation ray, rather than the full original ray. A continuation ray starts from the previous point of intersection and extends in the direction of the original ray. These steps help counter divergence that would occur if a single shader program that inlined the intersection and any hit shaders were executed.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Skyler Jonathon Saleh
  • Publication number: 20200193685
    Abstract: Described herein is a technique for performing ray-triangle intersection test in a manner that produces watertight results. The technique involves translating the coordinates of the triangle such that the origin is at the origin of the ray. The technique involves projecting the coordinate system into the viewspace of the ray. The technique then involves calculating barycentric coordinates and interpolating the barycentric coordinates to get a time of intersect. The signs of the barycentric coordinates indicate whether a hit occurs. The above calculations are performed with a non-directed floating point rounding mode to provide watertightness. A non-directed rounding mode is one in which the mantissa of a rounded number is rounded in a manner that is not dependent on the sign of the number.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Ruijin Wu
  • Publication number: 20200111248
    Abstract: A technique for compressing an original image is disclosed. According to the technique, an original image is obtained and a delta-encoded image is generated based on the original image. Next, a segregated image is generated based on the delta-encoded image and then the segregated image is compressed to produce a compressed image. The segregated image is generated because the segregated image may be compressed more efficiently than the original image and the delta image.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 9, 2020
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ruijin Wu, Skyler Jonathon Saleh, Christopher J. Brennan, Kei Ming Kwong, Anthony Hung-Cheong Chan
  • Patent number: 10529118
    Abstract: A technique for compressing an original image is disclosed. According to the technique, an original image is obtained and a delta-encoded image is generated based on the original image. Next, a segregated image is generated based on the delta-encoded image and then the segregated image is compressed to produce a compressed image. The segregated image is generated because the segregated image may be compressed more efficiently than the original image and the delta image.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 7, 2020
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ruijin Wu, Skyler Jonathon Saleh, Christopher J. Brennan, Kei Ming Kwong, Anthony Hung-Cheong Chan
  • Publication number: 20200005514
    Abstract: A technique for compressing an original image is disclosed. According to the technique, an original image is obtained and a delta-encoded image is generated based on the original image. Next, a segregated image is generated based on the delta-encoded image and then the segregated image is compressed to produce a compressed image. The segregated image is generated because the segregated image may be compressed more efficiently than the original image and the delta image.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ruijin Wu, Skyler Jonathon Saleh, Christopher J. Brennan, Kei Ming Kwong, Anthony Hung-Cheong Chan
  • Publication number: 20200004585
    Abstract: Techniques for executing shader programs with divergent control flow on a single instruction multiple data (“SIMD”) processor are disclosed. These techniques includes detecting entry into a divergent section of a shader program and, for the work-items that enter the divergent section, placing a task entry into a task queue associated with the target of each work-item. The target is the destination, in code, of any particular work-item, and is also referred to as a code segment herein. The task queues store task entries for code segments generated by different (or the same) wavefronts. A command processor examines task lists and schedules wavefronts for execution by grouping together tasks in the same task list into wavefronts and launching those wavefronts. By grouping tasks from different wavefronts together for execution in the same front, serialization of execution is greatly reduced or eliminated.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Maxim V. Kazakov
  • Patent number: 10510185
    Abstract: A technique for performing rasterization and pixel shading with decoupled resolution is provided herein. The technique involves performing rasterization as normal to generate fine rasterization data and a set of (fine) quads. The quads are accumulated into a tile buffer and coarse quads are generated from the quads in the tile buffer based on a shading rate. The shading rate determines how many pixels of the fine quads are combined to generate coarse pixels of the coarse quads. Combination of fine pixels involves generating a single coarse pixel for each such fine pixel to be combined. The positions of the coarse pixels of the coarse quads are set based on the positions of the corresponding fine pixels. The coarse quads are shaded normally and the resulting shaded coarse quads are modified based on the fine rasterization data to generate shaded fine quads.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: December 17, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Skyler Jonathon Saleh, Christopher J. Brennan, Andrew S. Pomianowski, Ruijin Wu
  • Patent number: 10410313
    Abstract: This disclosure describes examples for determining an amount of foveation that is to be applied for rendering an image. The example techniques may use information indicative of a performance of a graphics processing unit (GPU) to determine the amount of foveation that is to be applied. The GPU may render an image based on the determined amount of foveation.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: September 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Skyler Jonathon Saleh, Maurice Franklin Ribble, David Rigel Garcia Garcia
  • Publication number: 20190197761
    Abstract: A texture processor based ray tracing accelerator method and system are described. The system includes a shader, texture processor (TP) and cache, which are interconnected. The TP includes a texture address unit (TA), a texture cache processor (TCP), a filter pipeline unit and a ray intersection engine. The shader sends a texture instruction which contains ray data and a pointer to a bounded volume hierarchy (BVH) node to the TA. The TCP uses an address provided by the TA to fetch BVH node data from the cache. The ray intersection engine performs ray-BVH node type intersection testing using the ray data and the BVH node data. The intersection testing results and indications for BVH traversal are returned to the shader via a texture data return path. The shader reviews the intersection results and the indications to decide how to traverse to the next BVH node.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Maxim V. Kazakov, Vineet Goel
  • Publication number: 20190066371
    Abstract: A technique for performing rasterization and pixel shading with decoupled resolution is provided herein. The technique involves performing rasterization as normal to generate fine rasterization data and a set of (fine) quads. The quads are accumulated into a tile buffer and coarse quads are generated from the quads in the tile buffer based on a shading rate. The shading rate determines how many pixels of the fine quads are combined to generate coarse pixels of the coarse quads. Combination of fine pixels involves generating a single coarse pixel for each such fine pixel to be combined. The positions of the coarse pixels of the coarse quads are set based on the positions of the corresponding fine pixels. The coarse quads are shaded normally and the resulting shaded coarse quads are modified based on the fine rasterization data to generate shaded fine quads.
    Type: Application
    Filed: August 25, 2017
    Publication date: February 28, 2019
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Christopher J. Brennan, Andrew S. Pomianowski, Ruijin Wu
  • Patent number: 10192280
    Abstract: A graphics processing unit (GPU) may rasterize a primitive into a plurality of samples, wherein vertices of the primitive are associated with VRS parameters. The GPU may determine a VRS quality group that comprises one or more sub regions of the plurality of samples based at least in part on the VRS parameters. The GPU may fragment shade a VRS tile that represents the VRS quality group, wherein the VRS tile comprises fewer samples than the VRS quality group. The GPU may amplify the stored VRS tile into shaded fragments that correspond to the VRS quality group.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Skyler Jonathon Saleh, Vineet Goel, Maurice Franklin Ribble, Andrew Evan Gruber