Abstract: A data path architecture and corresponding method of operation are disclosed that permit a first-in-first out (FIFO) buffer to immediately flush data—including potentially invalid initial byte(s)—upon receipt of a high-speed clock signal, and according to which, a delay difference between a data path clock signal and a high-speed clock signal is compensated for at a controller side by, for example, adjusting RE latency to discard/ignore the initially invalid bytes rather than by modifying FIFO depth or varying a number of delay stages in the high-speed clock signal path in order to satisfy the FIFO depth. Because FIFO depth is not used to absorb the clock signal delay difference, there is no need to modify the architecture (e.g., change the depth of a FIFO) to accommodate variation in the clock signal delay difference across different products/product generations, thereby providing high scalability.

Abstract: Systems and methods disclosed herein provide for selectively activating or deactivating one or more memory of a memory array, such that related data path logic of deactivated memory dies neither detects nor processes control signals or data signals for data operations. Examples of the systems and methods provided herein operate to detect a first enable signal at a memory die and detect a first data signal on input/output (I/O) receivers of the memory die. Responsive to detecting at least the first enable signal, a bit value encoded in the first data signal is latched to obtain a first bit pattern. A second bit pattern is obtained, and, based on a comparison of the first bit pattern to the second bit pattern, the I/O receivers of the memory die are activated.

Abstract: A data path architecture and corresponding method of operation are disclosed that permit a first-in-first out (FIFO) buffer to immediately flush data—including potentially invalid initial byte(s)—upon receipt of a high-speed clock signal, and according to which, a delay difference between a data path clock signal and a high-speed clock signal is compensated for at a controller side by, for example, adjusting RE latency to discard/ignore the initially invalid bytes rather than by modifying FIFO depth or varying a number of delay stages in the high-speed clock signal path in order to satisfy the FIFO depth. Because FIFO depth is not used to absorb the clock signal delay difference, there is no need to modify the architecture (e.g., change the depth of a FIFO) to accommodate variation in the clock signal delay difference across different products/product generations, thereby providing high scalability.

Abstract: A data storage system includes a storage medium including a plurality of memory cells; a storage controller in communication with the storage medium; and an electrical interface between the storage medium and the storage controller. The electrical interface includes an N-bit data bus; a data strobe; a command latch enable signal; and an address latch enable signal; wherein, while the command latch signal or the address latch enable signal is asserted, the storage medium is configured to: (i) receive command or address data via a subset of lines of the data bus; and (ii) latch the command or address data using the data strobe.

Abstract: A data storage system includes a storage medium including a plurality of memory cells; a storage controller in communication with the storage medium; and an electrical interface between the storage medium and the storage controller. The electrical interface includes an N-bit data bus; a data strobe; a command latch enable signal; and an address latch enable signal; wherein, while the command latch signal or the address latch enable signal is asserted, the storage medium is configured to: (i) receive command or address data via a subset of lines of the data bus; and (ii) latch the command or address data using the data strobe.

Abstract: A circuit comprising a non-volatile memory array, an Input/Output (IO) circuit, a decoder circuit, a control circuit, and a read/write circuit. The non-volatile memory array couples to an address decoder that identifies a location within the non-volatile memory array for a storage command. The IO circuit couples to a decoder circuit through a control bus. The decoder circuit decodes a command address and storage command from a fixed length command sequence received by the IO circuit over the data bus. The decoder circuit may include a serial-in parallel out (SIPO) circuit for decoding and parallel operation. The control circuit couples to the IO and decoder circuits and generates control signals to execute decoded storage commands. The read/write circuit couples to the non-volatile memory array and the control circuit. The read/write circuit transfers data between the non-volatile memory array and the IO circuit in response to the storage commands.

Abstract: A memory device includes a memory controller to transmit or receive input/output (“I/O”) data via an I/O signal, as well as transmit command data, address data, or parameter data via another signal in parallel with transmitting or receiving the I/O data. The memory device also includes a memory module communicably coupled to the memory controller. The memory module receives the command data, address data, or parameter data from the memory controller to perform an operation.

Abstract: A memory device includes a memory controller to transmit or receive input/output (“I/O”) data via an I/O signal, as well as transmit command data, address data, or parameter data via another signal in parallel with transmitting or receiving the I/O data. The memory device also includes a memory module communicably coupled to the memory controller. The memory module receives the command data, address data, or parameter data from the memory controller to perform an operation.

Abstract: A memory device includes receiving, by a memory module, a first combined signal and a second combined signal from a memory controller and decoding, by the memory module, the first combined signal and the second combined signal to obtain a first chip enable signal, a first address latch enable signal, and a first command latch enable signal. Upon decoding, the first command latch enable signal and the first address latch enable signal are received substantially simultaneously as the first chip enable signal to reduce a setup time.

Abstract: A memory device includes receiving, by a memory module, a first combined signal and a second combined signal from a memory controller and decoding, by the memory module, the first combined signal and the second combined signal to obtain a first chip enable signal, a first address latch enable signal, and a first command latch enable signal. Upon decoding, the first command latch enable signal and the first address latch enable signal are received substantially simultaneously as the first chip enable signal to reduce a setup time.

Abstract: Disclosed is a system including a memory timing calibration circuit to calibrate a strobe signal of a memory device and a method of calibrating the strobe signal. The memory timing calibration circuit includes a difference signal generator coupled to a strobe signal generator and an external control circuit. The difference signal generator is configured to generate a difference signal indicating a time difference between the strobe signal from the strobe signal generator and an external clock signal from the external control circuit. The memory timing calibration circuit further includes a delay circuit coupled to the difference signal generator and the external control circuit. The delay circuit is configured to generate a modified external clock signal by delaying the external clock signal by a delay determined based at least in part on the difference signal.