Patents by Inventor Soichi Homma

Soichi Homma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7141878
    Abstract: A semiconductor device is comprised of a semiconductor element having a low dielectric constant insulating film, first electrode pads and barrier metal layers; and a substrate having second electrode pads corresponding to the first electrode pads. The first electrode pads and the second electrode pads are connected via metal bumps. The barrier metal layers having a thickness in a range of 0.1 to 3 ?m are interposed between the metal bumps and the first electrode pads. Besides, when it is assumed that the barrier metal layers have a diameter D1, the second electrode pads have an opening diameter D2 and the metal bumps have a minimum pitch p, the diameter D1 of the barrier metal layers satisfies at least one of conditions of D1?D2 and D1=0.4 p to 0.7 p. Thus, the occurrence of a crack, peeling or the like due to the low dielectric constant insulating films can be retarded.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: November 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Soichi Homma
  • Publication number: 20050266668
    Abstract: A semiconductor device comprises a semiconductor element having first electrode pads and solder bumps, and a substrate having second electrode pads connected to the first electrode pads via the solder bumps. The semiconductor element has an insulating film with a low dielectric constant. The group of the solder bumps is provided with a solder bump in which a stress intensity factor K in a notch shape formed by the first electrode pad and the outline of the solder bump, when looking at a cross section through the center of the first electrode pad and the solder bump, is such that on the chip edge side it is less than or equal to its value on the chip center side. Thereby, cracking or delamination of the semiconductor element due to the insulating film with a low dielectric constant can be restrained.
    Type: Application
    Filed: May 26, 2005
    Publication date: December 1, 2005
    Inventors: Kanako Sawada, Toshitsune lijima, Soichi Homma
  • Publication number: 20050179131
    Abstract: A semiconductor device is comprised of a semiconductor element having a low dielectric constant insulating film, first electrode pads and barrier metal layers; and a substrate having second electrode pads corresponding to the first electrode pads. The first electrode pads and the second electrode pads are connected via metal bumps. The barrier metal layers having a thickness in a range of 0.1 to 3 ?m are interposed between the metal bumps and the first electrode pads. Besides, when it is assumed that the barrier metal layers have a diameter D1, the second electrode pads have an opening diameter D2 and the metal bumps have a minimum pitch p, the diameter D1 of the barrier metal layers satisfies at least one of conditions of D1?D2 and Dl=0.4 p to 0.7 p. Thus, the occurrence of a crack, peeling or the like due to the low dielectric constant insulating films can be retarded.
    Type: Application
    Filed: February 17, 2005
    Publication date: August 18, 2005
    Inventor: Soichi Homma
  • Publication number: 20050006789
    Abstract: A packaging assembly includes a substrate; chip-site lands disposed on the first surface; first solder balls connected to the chip-site lands; second solder balls connected to the first solder balls including solder materials having higher melting temperatures than the first solder balls; a semiconductor chip having a plurality of bonding pads connected to the second solder balls on a surface of the semiconductor chip; and an underfill resin disposed around the first and second solder balls.
    Type: Application
    Filed: July 30, 2004
    Publication date: January 13, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akira Tomono, Soichi Homma
  • Publication number: 20040253803
    Abstract: A packaging assembly includes a substrate; chip-site lands disposed on the first surface; first solder balls connected to the chip-site lands; second solder balls connected to the first solder balls including solder materials having higher melting temperatures than the first solder balls; a semiconductor chip having a plurality of bonding pads connected to the second solder balls on a surface of the semiconductor chip; and an underfill resin disposed around the first and second solder balls.
    Type: Application
    Filed: October 27, 2003
    Publication date: December 16, 2004
    Inventors: Akira Tomono, Soichi Homma
  • Publication number: 20040238955
    Abstract: After a copper diffusion preventing film 4 is formed on a copper pad 1, a barrier metal including a titanium film 5, a nickel film 6, and a palladium film 7 is formed on the copper diffusion preventing film 4. The copper diffusion preventing film formed on the copper pad suppresses diffusion of copper. Even when a solder bump is formed on the copper pad, diffusion of tin in the solder and copper is suppressed. This prevents formation of an intermetallic compound between copper and tin, so no interface de-adhesion or delamination occurs and a highly reliable connection is obtained. This structure can be realized by a simple fabrication process unlike a method of forming a thick barrier metal by electroplating. In this invention, high shear strength can be ensured by connecting a solder bump, gold wire, or gold bump to a copper pad without increasing the number of fabrication steps.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 2, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Soichi Homma, Masahiro Miyata, Hirokazu Ezawa
  • Publication number: 20040222522
    Abstract: A semiconductor device includes a semiconductor chip having a semiconductor element or an integrated circuit formed in the semiconductor chip, a low dielectric constant insulating film formed on a surface of the semiconductor chip, and a plurality of bump electrodes being provided on the surface of the semiconductor chip, a wiring board having a plurality of connecting electrodes being electrically connected to the bump electrodes, and a resin molding filled in a space between the semiconductor chip and the wiring board, the electrically connected bump electrodes and the connecting electrodes being arranged in the space, wherein the resin molding is formed of a resin having a flux function and changed from liquid to solid when the bump electrodes are in a molten state.
    Type: Application
    Filed: March 12, 2004
    Publication date: November 11, 2004
    Inventor: Soichi Homma
  • Patent number: 6798050
    Abstract: After a copper diffusion preventing film 4 is formed on a copper pad 1, a barrier metal including a titanium film 5, a nickel film 6, and a palladium film 7 is formed on the copper diffusion preventing film 4. The copper diffusion preventing film formed on the copper pad suppresses diffusion of copper. Even when a solder bump is formed on the copper pad, diffusion of tin in the solder and copper is suppressed. This prevents formation of an intermetallic compound between copper and tin, so no interface de-adhesion or delamination occurs and a highly reliable connection is obtained. This structure can be realized by a simple fabrication process unlike a method of forming a thick barrier metal by electroplating. In this invention, high shear strength can be ensured by connecting a solder bump, gold wire, or gold bump to a copper pad without increasing the number of fabrication steps.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: September 28, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Homma, Masahiro Miyata, Hirokazu Ezawa
  • Patent number: 6569752
    Abstract: The present semiconductor element comprises a semiconductor substrate, a wiring pad formed thereon, a layer of barrier metal formed thereon, an intermetallic compound Ag3Sn formed thereon, and a protruded electrode consisting of low-melting metal formed thereon. In addition, a fabricating method of a semiconductor element comprises the steps of forming a wiring pad on a semiconductor substrate, forming a layer of barrier metal thereon, forming a metallic layer containing Ag thereon, forming a layer of low-melting metal containing Sn thereon, and melting the layer of low-melting metal containing Sn to form a protruded electrode and simultaneously to form an intermetallic compound Ag3Sn at an interface between the metallic layer containing Ag and the layer of low-melting metal containing Sn. Thus, with Pb-free solder, a semiconductor element of high reliability can be obtained.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: May 27, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Homma, Masahiro Miyata, Hirokazu Ezawa, Junichiro Yoshioka, Hiroaki Inoue, Tsuyoshi Tokuoka