Abstract: A semiconductor manufacturing device has an upper cover configured to be arranged above top surface of unshielded semiconductor device which are mounted on a tray placed on a carrier to go through electromagnetic shielding, and a displacement detector configured to detect an abnormality when the upper cover is raised by at least one of the semiconductor device which is brought into contact with a bottom surface of the upper cover.

Abstract: According to one embodiment, a semiconductor device includes a substrate. A semiconductor chip is disposed on a first surface of the substrate. The semiconductor chip is covered with a sealing material. A front surface and a side surface of the sealing material are covered with a conductive film. On an outer edge of a substrate-side of the semiconductor device, a step or a trench is formed.

Abstract: A semiconductor manufacturing device has a conveyor configured to convey a tray having an unshielded semiconductor device mounted thereon to go through electromagnetic shielding, and a controller configured to control the conveyor. The controller performs control to take out the tray from a tray supply storage storing trays each having an unshielded semiconductor device mounted thereon to go through the electromagnetic shielding, place the tray on a carrier, and convey this carrier to a sputtering device which coats the unshielded semiconductor device with a sputtering material for the electromagnetic shielding, and the controller performs control to take out, from the sputtering device, the carrier having the tray placed thereon with an electromagnetically shielded semiconductor device being mounted on the tray, convey the tray, pick up the tray having the electromagnetically shielded semiconductor device mounted thereon from the carrier, and store the tray in the tray supply storage.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a sealing resin layer containing an inorganic filler so as to seal a semiconductor chip, removing a portion of the surface of the sealing resin layer by dry etching such that a portion of the inorganic filler is exposed, and forming a shield layer so as to cover at least the sealing resin layer.

Abstract: A semiconductor device includes a conductive shield layer that has a first portion covering a surface of a sealing resin layer and a second portion covering side surfaces of the sealing resin layer and side surfaces of the substrate. Portions of wiring layers, including a grounding wire, on or in the substrate have cut planes which are exposed to the side surfaces of the substrate and spread out in a thickness direction of the substrate. A cut plane of the grounding wire is electrically connected to the shield layer. An area of the cut plane of the grounding wire is larger than an area of a cross section of the grounding wire parallel to, and inward of the substrate from, the cut plane of the grounding wire.

Abstract: A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals.

Abstract: In a semiconductor device manufacturing method, a first resin layer with optical transmission restrained is formed on a supporting substrate and a second resin layer made of thermoplastic resin is formed on the first resin layer. An insulating layer and a wiring layer are formed on the second resin layer and a first semiconductor chip is mounted on the wiring layer. The supporting substrate is separated by irradiating the first resin layer with a laser beam, and the second resin layer is removed.

Abstract: According to an embodiment, a separation layer and a wiring layer having an organic insulating film formed of a resin material and a metal wiring are sequentially formed on a support substrate. Regions of the organic insulating film corresponding to dicing regions are removed. Plural semiconductor chips are mounted on the wiring layer. A sealing resin layer is formed on the separation layer. The sealing resin layer is formed to cover edge surfaces of the device forming regions. The support substrate is separated from a resin sealing body having the wiring layer, the plural semiconductor chips and the sealing resin layer. The resin sealing body is cut according to the dicing regions to cingulate a structure configuring a semiconductor device.

Abstract: A resin layer made of thermoplastic resin is formed on a supporting substrate, and then, an insulating layer is formed on the first resin layer. Then, an interlayer connector is formed through the insulating layer and then, a wiring layer is formed on the first resin layer so as to be electrically connected with the interlayer connector. Thereafter, a first semiconductor chip is mounted on the wiring layer. Then, the first resin layer is heated so that the supporting substrate and the insulating layer are relatively shifted one another to shear the first resin layer, thereby separating the supporting substrate and the insulating layer and forming a semiconductor device.

Abstract: According to one embodiment, a method of fabricating a semiconductor device is disclosed. The method can include forming a debonding layer constituted with a thermoplastic resin on a supporting material, and forming an insulating layer constituted with a thermosetting resin including a solvent dissolving the thermoplastic resin on the debonding layer.

Abstract: A resin layer is formed on a support substrate. An intermediate structure body is formed on the resin layer. The support substrate is fixed to a first unit configured to fix and heat. The intermediate structure body is fixed to a second unit configured to fix and heat. The support substrate and the intermediate structure body are heated by the first unit or the second unit, so as to soften the resin layer. The second unit is moved with respect to the first unit along each of a plurality of line segments or a curve, so as to enlarge a distance between a center of the support substrate and a center of the intermediate structure body as the second unit moves, while the support substrate and the intermediate structure body being kept in the horizontal state, and until the support substrate and the intermediate structure body are separated.

Abstract: A resin layer made of thermoplastic resin is formed on a supporting substrate, and then, an insulating layer is formed on the first resin layer. Then, an interlayer connector is formed through the insulating layer and then, a wiring layer is formed on the first resin layer so as to be electrically connected with the interlayer connector. Thereafter, a first semiconductor chip is mounted on the wiring layer. Then, the first resin layer is heated so that the supporting substrate and the insulating layer are relatively shifted one another to shear the first resin layer, thereby separating the supporting substrate and the insulating layer and forming a semiconductor device.

Abstract: A packaging assembly includes a substrate; chip-site lands disposed on the first surface; first solder balls connected to the chip-site lands; second solder balls connected to the first solder balls including solder materials having higher melting temperatures than the first solder balls; a semiconductor chip having a plurality of bonding pads connected to the second solder balls on a surface of the semiconductor chip; and an underfill resin disposed around the first and second solder balls.

Abstract: A semiconductor device is comprised of a semiconductor element having a low dielectric constant insulating film, first electrode pads and barrier metal layers; and a substrate having second electrode pads corresponding to the first electrode pads. The first electrode pads and the second electrode pads are connected via metal bumps. The barrier metal layers having a thickness in a range of 0.1 to 3 ?m are interposed between the metal bumps and the first electrode pads. Besides, when it is assumed that the barrier metal layers have a diameter D1, the second electrode pads have an opening diameter D2 and the metal bumps have a minimum pitch p, the diameter D1 of the barrier metal layers satisfies at least one of conditions of D1?D2 and D1=0.4 p to 0.7 p. Thus, the occurrence of a crack, peeling or the like due to the low dielectric constant insulating films can be retarded.

Abstract: A semiconductor device comprises a semiconductor element having first electrode pads and solder bumps, and a substrate having second electrode pads connected to the first electrode pads via the solder bumps. The semiconductor element has an insulating film with a low dielectric constant. The group of the solder bumps is provided with a solder bump in which a stress intensity factor K in a notch shape formed by the first electrode pad and the outline of the solder bump, when looking at a cross section through the center of the first electrode pad and the solder bump, is such that on the chip edge side it is less than or equal to its value on the chip center side. Thereby, cracking or delamination of the semiconductor element due to the insulating film with a low dielectric constant can be restrained.

Abstract: A semiconductor device is comprised of a semiconductor element having a low dielectric constant insulating film, first electrode pads and barrier metal layers; and a substrate having second electrode pads corresponding to the first electrode pads. The first electrode pads and the second electrode pads are connected via metal bumps. The barrier metal layers having a thickness in a range of 0.1 to 3 ?m are interposed between the metal bumps and the first electrode pads. Besides, when it is assumed that the barrier metal layers have a diameter D1, the second electrode pads have an opening diameter D2 and the metal bumps have a minimum pitch p, the diameter D1 of the barrier metal layers satisfies at least one of conditions of D1?D2 and Dl=0.4 p to 0.7 p. Thus, the occurrence of a crack, peeling or the like due to the low dielectric constant insulating films can be retarded.

Abstract: A packaging assembly includes a substrate; chip-site lands disposed on the first surface; first solder balls connected to the chip-site lands; second solder balls connected to the first solder balls including solder materials having higher melting temperatures than the first solder balls; a semiconductor chip having a plurality of bonding pads connected to the second solder balls on a surface of the semiconductor chip; and an underfill resin disposed around the first and second solder balls.

Abstract: A packaging assembly includes a substrate; chip-site lands disposed on the first surface; first solder balls connected to the chip-site lands; second solder balls connected to the first solder balls including solder materials having higher melting temperatures than the first solder balls; a semiconductor chip having a plurality of bonding pads connected to the second solder balls on a surface of the semiconductor chip; and an underfill resin disposed around the first and second solder balls.

Abstract: After a copper diffusion preventing film 4 is formed on a copper pad 1, a barrier metal including a titanium film 5, a nickel film 6, and a palladium film 7 is formed on the copper diffusion preventing film 4. The copper diffusion preventing film formed on the copper pad suppresses diffusion of copper. Even when a solder bump is formed on the copper pad, diffusion of tin in the solder and copper is suppressed. This prevents formation of an intermetallic compound between copper and tin, so no interface de-adhesion or delamination occurs and a highly reliable connection is obtained. This structure can be realized by a simple fabrication process unlike a method of forming a thick barrier metal by electroplating. In this invention, high shear strength can be ensured by connecting a solder bump, gold wire, or gold bump to a copper pad without increasing the number of fabrication steps.

Abstract: A semiconductor device is comprised of a semiconductor element having a low dielectric constant insulating film, first electrode pads and barrier metal layers; and a substrate having second electrode pads corresponding to the first electrode pads. The first electrode pads and the second electrode pads are connected via metal bumps. The barrier metal layers having a thickness in a range of 0.1 to 3 ?m are interposed between the metal bumps and the first electrode pads. Besides, when it is assumed that the barrier metal layers have a diameter D1, the second electrode pads have an opening diameter D2 and the metal bumps have a minimum pitch p, the diameter D1 of the barrier metal layers satisfies at least one of conditions of D1?D2 and D1=0.4 p to 0.7 p. Thus, the occurrence of a crack, peeling or the like due to the low dielectric constant insulating films can be retarded.