Patents by Inventor Soichi Kobayashi
Soichi Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11927516Abstract: A sample scraping method and a sample scraping device capable of efficiently scraping and collecting a biological tissue section without waste while suppressing contamination is provided. In a sample scraping method for scraping and collecting a biological tissue section held on a slide, the FFPE section held on the slide is heated, and the heated FFPE section is scraped by a blade such that the FFPE section that has been scraped off and remains on the blade is collected in a container.Type: GrantFiled: February 15, 2022Date of Patent: March 12, 2024Assignee: SYSMEX CORPORATIONInventors: Soichi Oue, Yutaka Maeda, Junyi Ding, Takayuki Koshihara, Hironori Kobayashi, Yasuhiro Kouchi
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Patent number: 10331204Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: GrantFiled: March 8, 2018Date of Patent: June 25, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
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Patent number: 10317981Abstract: A data processing device includes a load circuit including a central processing unit and operated by supplied electric power, a step-down power supply circuit stepping down an external power supply voltage and including an output node coupled to the load circuit, the step-down power supply circuit including a first step-down unit stepping down the external power supply voltage, and a bias current control circuit controlling a magnitude of bias current flowing through an auxiliary path from the output node to a ground, the auxiliary path is separate from a path to the load circuit, and a control circuit increasing the magnitude of the bias current, prior to a change of an operation state of the load circuit by which a relatively large change occurs to an amount of current consumed by the load circuit.Type: GrantFiled: December 6, 2016Date of Patent: June 11, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
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Publication number: 20180196500Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: ApplicationFiled: March 8, 2018Publication date: July 12, 2018Inventors: Yoshinori TOKIOKA, Soichi KOBAYASHI, Akira OIZUMI
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Patent number: 9946332Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: GrantFiled: February 22, 2017Date of Patent: April 17, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
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Publication number: 20170160792Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: ApplicationFiled: February 22, 2017Publication date: June 8, 2017Inventors: Yoshinori TOKIOKA, Soichi KOBAYASHI, Akira OIZUMI
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Patent number: 9612644Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: GrantFiled: September 3, 2015Date of Patent: April 4, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
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Publication number: 20170083080Abstract: A data processing device includes a load circuit including a central processing unit and operated by supplied electric power, a step-down power supply circuit stepping down an external power supply voltage and including an output node coupled to the load circuit, the step-down power supply circuit including a first step-down unit stepping down the external power supply voltage, and a bias current control circuit controlling a magnitude of bias current flowing through an auxiliary path from the output node to a ground, the auxiliary path is separate from a path to the load circuit, and a control circuit increasing the magnitude of the bias current, prior to a change of an operation state of the load circuit by which a relatively large change occurs to an amount of current consumed by the load circuit.Type: ApplicationFiled: December 6, 2016Publication date: March 23, 2017Inventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
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Patent number: 9529402Abstract: A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.Type: GrantFiled: September 2, 2010Date of Patent: December 27, 2016Assignee: Renesas Electronics CorporationInventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
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Publication number: 20150378426Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: ApplicationFiled: September 3, 2015Publication date: December 31, 2015Inventors: Yoshinori TOKIOKA, Soichi KOBAYASHI, Akira OIZUMI
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Patent number: 9166601Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: GrantFiled: September 25, 2013Date of Patent: October 20, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
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Patent number: 9130574Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: GrantFiled: September 25, 2013Date of Patent: September 8, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
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Patent number: 8860392Abstract: A semiconductor device includes a voltage generating circuit, a first switch, and a charging circuit. The voltage generating circuit generates a voltage for output and has a function to adjust a magnitude of the voltage to be generated. A first switch has a first conduction terminal and a second conduction terminal that are brought into conduction with each other in an ON state, and the first conduction terminal is connected to an output node of the voltage generating circuit via a first line. The charging circuit charges a second line connected to the second conduction terminal of the first switch.Type: GrantFiled: February 7, 2012Date of Patent: October 14, 2014Assignee: Renesas Electronics CorporationInventors: Hiromu Kinoshita, Shinsuke Yoshimura, Akira Suzuki, Akira Oizumi, Soichi Kobayashi
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Publication number: 20140084973Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.Type: ApplicationFiled: September 25, 2013Publication date: March 27, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
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Publication number: 20130207634Abstract: A semiconductor device includes a voltage generating circuit, a first switch, and a charging circuit. The voltage generating circuit generates a voltage for output and has a function to adjust a magnitude of the voltage to be generated. A first switch has a first conduction terminal and a second conduction terminal that are brought into conduction with each other in an ON state, and the first conduction terminal is connected to an output node of the voltage generating circuit via a first line. The charging circuit charges a second line connected to the second conduction terminal of the first switch.Type: ApplicationFiled: February 7, 2012Publication date: August 15, 2013Inventors: Hiromu Kinoshita, Shinsuke Yoshimura, Akira Suzuki, Akira Oizumi, Soichi Kobayashi
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Publication number: 20130159746Abstract: A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.Type: ApplicationFiled: September 2, 2010Publication date: June 20, 2013Applicant: Renesas Electronics CorporationInventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
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Patent number: 8350791Abstract: In displaying image data received from a camera module on a display device such as a view finder, image data having a size suited for display from an image size conversion circuit is displayed via line memories included in a signal-for-display generation circuit. Vertical synchronization in an image data storage including these line memories is established by initializing a reading address in accordance with a frame head pixel indication and a reading completion indication of one line in the line memories. It is possible to reduce power consumption of an image display system for displaying an image of a imaging subject.Type: GrantFiled: December 28, 2007Date of Patent: January 8, 2013Assignee: Renesas Electronics CorporationInventors: Masaru Takahashi, Soichi Kobayashi, Toshiyuki Maruyama
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Patent number: 7457996Abstract: In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to “0” when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to “1” when once the comparison result for the corresponding column indicates difference.Type: GrantFiled: August 4, 2003Date of Patent: November 25, 2008Assignee: Renesas Technology Corp.Inventors: Soichi Kobayashi, Yoshiaki Yamazaki, Yukihiko Shimazu
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Publication number: 20080288836Abstract: In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to “0” when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to “1” when once the comparison result for the corresponding column indicates difference.Type: ApplicationFiled: July 17, 2008Publication date: November 20, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Soichi Kobayashi, Yoshiaki Yamazaki, Yukihiko Shimazu
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Publication number: 20080165268Abstract: In displaying image data received from a camera module on a display device such as a view finder, image data having a size suited for display from an image size conversion circuit is displayed via line memories included in a signal-for-display generation circuit. Vertical synchronization in an image data storage including these line memories is established by initializing a reading address in accordance with a frame head pixel indication and a reading completion indication of one line in the line memories. It is possible to reduce power consumption of an image display system for displaying an image of a imaging subject.Type: ApplicationFiled: December 28, 2007Publication date: July 10, 2008Inventors: Masaru Takahashi, Soichi Kobayashi, Toshiyuki Maruyama