Patents by Inventor Soichi Kobayashi

Soichi Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10331204
    Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: June 25, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
  • Patent number: 10317981
    Abstract: A data processing device includes a load circuit including a central processing unit and operated by supplied electric power, a step-down power supply circuit stepping down an external power supply voltage and including an output node coupled to the load circuit, the step-down power supply circuit including a first step-down unit stepping down the external power supply voltage, and a bias current control circuit controlling a magnitude of bias current flowing through an auxiliary path from the output node to a ground, the auxiliary path is separate from a path to the load circuit, and a control circuit increasing the magnitude of the bias current, prior to a change of an operation state of the load circuit by which a relatively large change occurs to an amount of current consumed by the load circuit.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: June 11, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
  • Publication number: 20190141988
    Abstract: A perfusion device and a perfusion method can allocate two routes of perfusate inflow pathways and two routes of perfusate outflow pathways for a liver graft. The perfusate inflow pathways have perfusate inflow cannulas connected respectively to the portal vein and the hepatic artery. The perfusate outflow pathways have perfusate outflow cannulas connected respectively to the suprahepatic inferior vena cava and the infrahepatic inferior vena cava. Perfusate is allowed to enter the liver from the perfusate inflow cannulas, and the perfusate in the liver is allowed to drain off from the perfusate outflow cannulas. This significantly shortens the time length of the liver graft being in an ischemic condition when the liver is removed or transplanted. That is, the onset of disorder in the liver graft can be suppressed. This increases the success rate of liver transplantation. Thus, deterioration of organ grafts during surgery is prevented in organ transplantation surgery that requires long hours.
    Type: Application
    Filed: May 19, 2017
    Publication date: May 16, 2019
    Inventors: Eiji KOBAYASHI, Takashi TSUJI, Jun ISHIKAWA, Soichi NADAHARA, Syuhei YOSHIMOTO, Shinji TORAI
  • Publication number: 20180196500
    Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.
    Type: Application
    Filed: March 8, 2018
    Publication date: July 12, 2018
    Inventors: Yoshinori TOKIOKA, Soichi KOBAYASHI, Akira OIZUMI
  • Patent number: 9946332
    Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: April 17, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
  • Publication number: 20170160792
    Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Inventors: Yoshinori TOKIOKA, Soichi KOBAYASHI, Akira OIZUMI
  • Patent number: 9612644
    Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: April 4, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
  • Publication number: 20170083080
    Abstract: A data processing device includes a load circuit including a central processing unit and operated by supplied electric power, a step-down power supply circuit stepping down an external power supply voltage and including an output node coupled to the load circuit, the step-down power supply circuit including a first step-down unit stepping down the external power supply voltage, and a bias current control circuit controlling a magnitude of bias current flowing through an auxiliary path from the output node to a ground, the auxiliary path is separate from a path to the load circuit, and a control circuit increasing the magnitude of the bias current, prior to a change of an operation state of the load circuit by which a relatively large change occurs to an amount of current consumed by the load circuit.
    Type: Application
    Filed: December 6, 2016
    Publication date: March 23, 2017
    Inventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
  • Patent number: 9529402
    Abstract: A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: December 27, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
  • Publication number: 20150378426
    Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.
    Type: Application
    Filed: September 3, 2015
    Publication date: December 31, 2015
    Inventors: Yoshinori TOKIOKA, Soichi KOBAYASHI, Akira OIZUMI
  • Patent number: 9166601
    Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: October 20, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
  • Patent number: 9130574
    Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: September 8, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
  • Patent number: 8860392
    Abstract: A semiconductor device includes a voltage generating circuit, a first switch, and a charging circuit. The voltage generating circuit generates a voltage for output and has a function to adjust a magnitude of the voltage to be generated. A first switch has a first conduction terminal and a second conduction terminal that are brought into conduction with each other in an ON state, and the first conduction terminal is connected to an output node of the voltage generating circuit via a first line. The charging circuit charges a second line connected to the second conduction terminal of the first switch.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: October 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiromu Kinoshita, Shinsuke Yoshimura, Akira Suzuki, Akira Oizumi, Soichi Kobayashi
  • Publication number: 20140084973
    Abstract: A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 27, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Tokioka, Soichi Kobayashi, Akira Oizumi
  • Publication number: 20130207634
    Abstract: A semiconductor device includes a voltage generating circuit, a first switch, and a charging circuit. The voltage generating circuit generates a voltage for output and has a function to adjust a magnitude of the voltage to be generated. A first switch has a first conduction terminal and a second conduction terminal that are brought into conduction with each other in an ON state, and the first conduction terminal is connected to an output node of the voltage generating circuit via a first line. The charging circuit charges a second line connected to the second conduction terminal of the first switch.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 15, 2013
    Inventors: Hiromu Kinoshita, Shinsuke Yoshimura, Akira Suzuki, Akira Oizumi, Soichi Kobayashi
  • Publication number: 20130159746
    Abstract: A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.
    Type: Application
    Filed: September 2, 2010
    Publication date: June 20, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
  • Patent number: 8350791
    Abstract: In displaying image data received from a camera module on a display device such as a view finder, image data having a size suited for display from an image size conversion circuit is displayed via line memories included in a signal-for-display generation circuit. Vertical synchronization in an image data storage including these line memories is established by initializing a reading address in accordance with a frame head pixel indication and a reading completion indication of one line in the line memories. It is possible to reduce power consumption of an image display system for displaying an image of a imaging subject.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masaru Takahashi, Soichi Kobayashi, Toshiyuki Maruyama
  • Patent number: 7457996
    Abstract: In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to “0” when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to “1” when once the comparison result for the corresponding column indicates difference.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: November 25, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Soichi Kobayashi, Yoshiaki Yamazaki, Yukihiko Shimazu
  • Publication number: 20080288836
    Abstract: In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to “0” when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to “1” when once the comparison result for the corresponding column indicates difference.
    Type: Application
    Filed: July 17, 2008
    Publication date: November 20, 2008
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Soichi Kobayashi, Yoshiaki Yamazaki, Yukihiko Shimazu
  • Publication number: 20080165268
    Abstract: In displaying image data received from a camera module on a display device such as a view finder, image data having a size suited for display from an image size conversion circuit is displayed via line memories included in a signal-for-display generation circuit. Vertical synchronization in an image data storage including these line memories is established by initializing a reading address in accordance with a frame head pixel indication and a reading completion indication of one line in the line memories. It is possible to reduce power consumption of an image display system for displaying an image of a imaging subject.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 10, 2008
    Inventors: Masaru Takahashi, Soichi Kobayashi, Toshiyuki Maruyama