Patents by Inventor Soichi Kobayashi

Soichi Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040184328
    Abstract: In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to “0” when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to “1” when once the comparison result for the corresponding column indicates difference.
    Type: Application
    Filed: August 4, 2003
    Publication date: September 23, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Soichi Kobayashi, Yoshiaki Yamazaki, Yukihiko Shimazu
  • Patent number: 6433594
    Abstract: A signal output circuit includes a first NMOS transistor that supplies the potential of its drain as output data to an output terminal that has been pulled up to a high power source voltage. This signal output circuit includes a second NMOS transistor having input to its gate a control signal that becomes a high logical level when there is no power supplied, and having its drain connected to the gate of the first NMOS transistor.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: August 13, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Soichi Kobayashi
  • Publication number: 20020036521
    Abstract: A signal output circuit is equipped with a first NMOS transistor that applies a potential of its drain as output data to an output terminal that has been pulled up to a high power source voltage at the outside. This signal output circuit is provided with a second NMOS transistor having input to its gate a control signal that becomes high logical level when there is no power supply and having its drain connected to a gate of the first NMOS transistor.
    Type: Application
    Filed: February 28, 2001
    Publication date: March 28, 2002
    Inventor: Soichi Kobayashi
  • Patent number: 5151289
    Abstract: Frozen instant cooking noodles having a cross-sectional void space percent of 40 to 80% which are capable of uniformly thawing by heat in a very short time to provide a fully cooked noodles having good texture for eating are produced by subjecting noodles to .alpha. conversion so as to control a yield of the noodles within the range of 200 to 280%, quickly cooling the .alpha. converted noodles in cold water at 0.degree. to 5.degree. C., arranging individual strings of the noodle at random to form a noodle lump and freezing the lump.
    Type: Grant
    Filed: December 21, 1990
    Date of Patent: September 29, 1992
    Assignees: Nisshin Flour Milling Co., Ltd., MA MA-Macaroni Co., Ltd.
    Inventors: Ryutaro Ozawa, Tomoya Hayakawa, Noriko Kato, Soichi Kobayashi, Seisaku Fuse
  • Patent number: 3957474
    Abstract: A method for manufacturing a glass core rod and a cladding layer clothing the glass core rod applied successively or continuously by using a carbon dioxide gas laser. A refractory mandrel is heated by means of carbon dioxide gas laser irradiation and a mixed gas of oxygen and pure silicon tetrachloride vapor and a dopant compound vapor is ejected to the refractory mandrel so as to deposit silicon oxide and oxide of the dopant compound on the mandrel and to form a glass core by fusing it. Further heating is applied by irradiation by the carbon dioxide laser beam on the glass core and a mixed gas oxygen and pure silicon tetrachloride vapor and a dopant compound vapor or of oxygen gas and pure silicon tetrachloride vapor to deposit silicon oxide and oxide of the dopant compound or silicon oxide on the glass core to form a cladding layer of fused silica or fused silica containing the dopant.
    Type: Grant
    Filed: April 17, 1975
    Date of Patent: May 18, 1976
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Soichi Kobayashi, Tatsuo Izawa