Abstract: A D-class amplifier that can suppress noise generated when a D-class amplification operation is started/stopped. When a D-class amplification operation is started/stopped, the pulse widths and pulse interval of output signals Pout1, Pout2 are gradually changed, so it is possible to prevent a large variation in the signal fed as a differential signal of output signals Pout1, Pout2 to the load, and it is possible to reduce noise. That is, by gradually changing the pulse interval while keeping the pulse widths of output signals Pout1, Pout2 constant, it is possible to suppress variation in the relatively high frequency component corresponding to the component of the pulse signal. Also, by gradually changing the widths of output signals Pout1, Pout2 while keeping the pulse interval constant, it is possible to suppress variation in the relatively low frequency component corresponding to the average value of the pulse signal.

Abstract: A voltage supply circuit and a circuit device can reduce the noise in the output of the circuit when the power to the circuit is turned on and off and can shorten the time required to start or stop the operation of the circuit. When the supply of power to signal processing part 10 is started or stopped, reference voltage Vref supplied to signal processing part 10 is varied continuously to reduce the high-frequency noise in the output of signal processing part 10. Also, when the setpoint value of the waveform of reference voltage Vref is generated by digital signal processing in voltage setting part 30, the desired waveform can be generated without being limited by the values of the circuit elements or the circuit configuration. The output noise of signal processing part 10 can be reduced, and the time that reference time Vref varies can be shortened.

Abstract: A D-class amplifier that can suppress noise generated when a D-class amplification operation is started/stopped. When a D-class amplification operation is started/stopped, the pulse widths and pulse interval of output signals Pout1, Pout2 are gradually changed, so it is possible to prevent a large variation in the signal fed as a differential signal of output signals Pout1, Pout2 to the load, and it is possible to reduce noise. That is, by gradually changing the pulse interval while keeping the pulse widths of output signals Pout1, Pout2 constant, it is possible to suppress variation in the relatively high frequency component corresponding to the component of the pulse signal. Also, by gradually changing the widths of output signals Pout1, Pout2 while keeping the pulse interval constant, it is possible to suppress variation in the relatively low frequency component corresponding to the average value of the pulse signal.

Abstract: A weight level generator is provided. Weight level generator W has plural weight generators 5-1-5-j. At least one of said plural weight generators is used at at least two different time rates. Also, a digital-to-analog converter (DAC) using said weight generators is equipped with a digital signal source, a weight controller, and a weight generator.

Abstract: The objective of the invention is to provide a class D amplifier that can reduce aliasing noise. The class D amplifier has D/A converter 10 that operates at the first sampling frequency, and PWM driver 3 that receives the output from D/A converter 10. Said PWM driver 3 operates at the second sampling frequency synchronized to the first sampling frequency. The second sampling frequency can be correlated to the delta wave frequency of the PWM driver. Also, synchronization of said first sampling frequency and said second sampling frequency can be carried out with one of said frequencies being an integer multiple of the other.

Abstract: The invention provides an improved dynamic element matching (DEM) device. The DEM device performs dynamic element matching processing at a second timing rate different from the first timing rate for the digital input. As an embodiment, the DEM device is composed of encoder 10 and feedback circuit 12. Said encoder 10 has two inputs and one output. Of the two inputs, one receives the digital input as the object for the DEM processing, and the other input receives the output of feedback circuit 12. Then, the digital output of the encoded result is generated. Said feedback circuit 12 has sampling rate converter 120 and loop filter 122 in order to perform DEM processing at a timing rate different from the timing rate for the digital input as the DEM processing object.

Abstract: A voltage supply circuit and a circuit device can reduce the noise in the output of the circuit when the power to the circuit is turned on and off and can shorten the time required to start or stop the operation of the circuit. When the supply of power to signal processing part 10 is started or stopped, reference voltage Vref supplied to signal processing part 10 is varied continuously to reduce the high-frequency noise in the output of signal processing part 10. Also, when the setpoint value of the waveform of reference voltage Vref is generated by digital signal processing in voltage setting part 30, the desired waveform can be generated without being limited by the values of the circuit elements or the circuit configuration. The output noise of signal processing part 10 can be reduced, and the time that reference time Vref varies can be shortened.

Abstract: A weight level generator is provided. Weight level generator W has plural weight generators 5-1-5-j. At least one of said plural weight generators is used at at least two different time rates. Also, a digital-to-analog converter (DAC) using said weight generators is equipped with a digital signal source, a weight controller, and a weight generator.

Abstract: The invention provides an improved dynamic element matching (DEM) device. The DEM device performs dynamic element matching processing at a second timing rate different from the first timing rate for the digital input. As an embodiment, the DEM device is composed of encoder 10 and feedback circuit 12. Said encoder 10 has two inputs and one output. Of the two inputs, one receives the digital input as the object for the DEM processing, and the other input receives the output of feedback circuit 12. Then, the digital output of the encoded result is generated. Said feedback circuit 12 has sampling rate converter 120 and loop filter 122 in order to perform DEM processing at a timing rate different from the timing rate for the digital input as the DEM processing object.

Abstract: Transient response generating circuit A has a first circuit 3 that generates transient response OUT1 in a first polarity direction, a second circuit 4 that generates transient response OUT2 in a second polarity direction opposite to the first polarity, and a transient response synthesizing circuit 6 that combines the transient response OUT1 in the first polarity direction and the transient response OUT2 in the second polarity direction to generate composite transient response OUTC.

Abstract: A digital encoder having a dynamic element matching (DEM) processor is divided into a master DEM circuit and N slave DEM circuits. The master DEM circuit encodes a multibit digital input signal (IN0) into parallel codes (C1) corresponding to the coefficient of a plurality of output nodes on the basis of a prescribed DEM algorithm. Each of the N slave DEM means (2) has 3 or more output nodes. Code (C1) from the master DEM circuit is encoded into parallel codes (C2) with the same weighting for each code and corresponding to the configuration of the 3 or more output nodes on the basis of a prescribed DEM algorithm, and the obtained parallel codes are output in parallel from 3 or more output nodes.

Abstract: The objective of the invention is to provide a class D amplifier that can reduce aliasing noise. The class D amplifier has D/A converter 10 that operates at the first sampling frequency, and PWM driver 3 that receives the output from D/A converter 10. Said PWM driver 3 operates at the second sampling frequency synchronized to the first sampling frequency. The second sampling frequency can be correlated to the delta wave frequency of the PWM driver. Also, synchronization of said first sampling frequency and said second sampling frequency can be carried out with one of said frequencies being an integer multiple of the other.

Abstract: Transient response generating circuit A has a first circuit 3 that generates transient response OUT1 in a first polarity direction, a second circuit 4 that generates transient response OUT2 in a second polarity direction opposite to the first polarity, and a transient response synthesizing circuit 6 that combines the transient response OUT1 in the first polarity direction and the transient response OUT2 in the second polarity direction to generate composite transient response OUTC.

Abstract: A digital encoder having a dynamic element matching (DEM) processor is divided into a master DEM circuit and N slave DEM circuits. The master DEM circuit encodes a multibit digital input signal (INO) into parallel codes (C1) corresponding to the coefficient of a plurality of output nodes on the basis of a prescribed DEM algorithm. Each of the N slave DEM means (2) has 3 or more output nodes. Code (C1) from the master DEM circuit is encoded into parallel codes (C2) with the same weighting for each code and corresponding to the configuration of the 3 or more output nodes on the basis of a prescribed DEM algorithm, and the obtained parallel codes are output in parallel from 3 or more output nodes.