Abstract: Structures, methods and materials for making multilayer circuit substrates are disclosed. The structures include bumped structures or microencapsulated conductive particles suitable for use in a lamination process to make a multilayer printed circuit substrate.

Abstract: Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

Abstract: A wiring substrate with reduced thermal expansion. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or a BGA package. The wiring substrate has a thermal expansion reduction insert in a thermal expansion stress region where the integrated circuit is mounted. The thermal expansion reduction insert may extend a selected distance from the edge or edges of the integrated circuit attachment area, or stop a selected distance from the edge or edges of the integrated circuit attachment area, or be essentially equal to the integrated circuit attachment area. The thermal expansion reduction insert reduces the thermal expansion of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly.

Abstract: A conductive composition, and articles and methods using the conductive composition are disclosed.

Abstract: A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.

Abstract: Methods for making circuit substrates and electrical assemblies are disclosed. A conductive composition is disposed between confronting conductive regions and can be cured to form a via structure. The conductive composition includes conductive particles and a carrier. The carrier can include a fluxing agent and an epoxy-functional resin having a viscosity of less than about 1000 centipoise at 25° C.

Abstract: Several inventive features for increasing the yield of substrate capacitors are disclosed. The inventive features relating to selective placement of insulating layers and patches around selected areas of the capacitor's main dielectric layer. These insulating layers and defects prevent certain manufacturing processing steps from creating pin-hole defects in the main dielectric layer. The inventive features are suitable for any type of material for the main dielectric layer, and are particularly suited to anodized dielectric layers.

Abstract: Methods of etching polyamic acid layers and the like are disclosed. In exemplary embodiments of the present invention, the polymeric acid layer to be etched is alternatively exposed to etchant solutions (etchants) and rinse solutions, where the etchant solutions are of relatively moderate alkalinity and the rinse solutions have a lower pH than the etchant solutions. The present invention enables polymeric acid layers to be developed with standard basic etchants at relatively moderate concentrations and at room temperature with little, if any, corrosion to any underlying metal layers. The present invention enables the more reliable and cleaner spin-spray processing method to be employed, thereby significantly increasing yields and reducing overall processing costs. The present invention also enables the etching of thick layers of polymeric acid without the need for special treatments, such as exposure to highly concentrated etchant solutions or high temperature processing conditions.

Abstract: A method of fabricating a multi-layer interconnected substrate structure. The inventive method includes forming a multi-layer structure from multiple, pre-fabricated power and/or signal substrates which are laminated together. A drill is then used to form a via through the surface of a ring-type pad down to a desired depth in the multi-layer structure. The via hole is cleaned and then filled with a conductive material. The via so formed between two or more substrates is self-aligned by using the ring pad(s). This contributes to an increased signal routing density compared to conventional methods.

Abstract: Methods and apparatuses for evenly polishing the entire polishing surface of a sample are described. One polishing apparatus of the present invention comprises: a platen having an upper surface upon which the sample surface is to be polished; a sample holder disposed opposite to the platen's upper surface, at least one of the platen and the sample holder being rotated about a first axis to effect polishing; a positioning means for changing the distance between the sample holder and the platen in response to a control signal; and a controller providing said control signal to the positioning means to control the operation of the positioning means during a polishing cycle, wherein the controller causes the positioning means to change the distance intermittently during the polishing cycle.

Abstract: Disclosed are venting hole structures suitable for AC grounding planes in multichip modules (MCMs) and the like. Such structures may be constructed from alternating layers of metal and dielectric materials, such as copper and polyimide, respectively. The venting structures according to the present invention are formed in the metal layers of grounding planes and enable gases trapped within the underlying dielectric layers to escape (so as to prevent delamination) without disturbing the function of the AC grounding plane to provide controlled impedance characteristics for signal lines disposed above and below the grounding plane.

Abstract: An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed through rigid segments and signals are routed through a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected.

Abstract: A chemical mechanical cleaning method utilizes an ammonium persulphate solution with simultaneous mechanical brushing to remove residual slurry particles from copper surfaces. The pH of the solution is selected to electrostatically repel charged slurry particles from the copper surface.

Abstract: Printed circuit substrates and electrical assemblies including a conductive composition are disclosed. The printed circuit substrate and the electrical assembly embodiments comprise a first conducting region and a second conducting region. A dielectric layer is disposed between the first and second conducting regions. An aperture is disposed in the dielectric layer and a via structure including the conductive composition is disposed in the aperture. The conductive composition is preferably in a cured state and electrically communicates with the first and second conducting regions. In preferred embodiments, the conductive composition comprises conductive particles in an amount of at least about 75 wt. % based on the weight of the composition. At least 50% by weight of the conductive particles have melting points of less than about 400.degree. C. The composition further includes a carrier including an epoxy-functional resin in an amount of at least about 50 wt.

Abstract: An interposer structure permits a differential transverse displacement of contact pads on opposite sides of the interposer to reduce thermal stresses when the interposer is bonded to contact pads of a chip and a substrate with different thermal coefficients of expansion. The effective elasticity of the interposer between top and bottom contact pads of the interposer is facilitated by perforations which define flap-like regions. A flexible trace couples top contact pads to bottom contact pads through a via while permitting substantial transverse relative displacement of the top and bottom contact pads in flap-like regions.

Abstract: Processes for forming conductive vias between circuit elements formed on either side of a flexible substrate are disclosed. In one embodiment, the inventive process starts with a flexible film polyimide substrate on each side of which is arranged a layer of copper. Both of the copper surfaces are coated with photoresist. Blind vias are then drilled through the top copper layer and substrate using a laser. The photoresist is then exposed (patterned). A plating operation is used to fill the vias with a conductive material. The resist is then developed and the line and pad structures on the surface of the copper layer are plated. The photoresist is then stripped. In a variation of this embodiment, the photoresist is imaged prior to drilling of the vias using a laser. In an alternative embodiment of the inventive process, a through hole is drilled instead of a blind via.

Abstract: A power distribution structure for a multichip module including, a base plate, a plurality of mesas arranged in a pattern are formed on the base plate, the mesas having electrically conductive upper surfaces which lie substantially in a single plane. A thin, conformal dielectric layer is formed over the exposed side surfaces of the mesas and the exposed surfaces of the support base and a conductive material is deposited over the dielectric material filling the area between and surrounding the mesas. The upper surfaces of the mesas and the upper surface of the conductive material surrounding the mesas lie in substantially one plane and are electrically isolated from each other by the dielectric material.

Abstract: Methods of forming a self aligned layers using a polishing step are disclosed. In an exemplary embodiment, a first layer of a first material is formed over an existing layer such that the first layer substantially conforms to and reproduces the pattern of the existing layer, with high and low portions whose locations correspond to the locations of the high and low portions, respectively, of the existing layer. Contrary to the practices of the polishing-planarization art, the first layer is formed such that its low portions are below the height of the high portions of the existing layer. Next, a relatively thin polish-stop layer of a second material is formed over the first layer such that the polish-stop layer substantially conforms to and reproduces the pattern of the first layer. The layers are then polished to remove the portions of the first layer and polish-stop layer which lie above the plane of the low portions of the polish-stop layer, and to provide a substantially flat surface.

Abstract: A weir with locks is used to encompass a platen used for chemical-mechanical polishing. The weir retains slurry that would otherwise be flung from a rotating platen because of centrifugal force. However, the locks permit some slurry to leave the platen, which enables the polishing process to include desirable flows of fresh slurry through the polishing pad to replenish polishing components and to flush out deleterious waste products. Additionally, the effective orifice size of the locks may be made a function of platen rotation rate. Polishing processes are possible in which the depth of the polishing slurry on the platen is a function of platen rotation rate.

Abstract: Methods of forming patterns in photo-sensitive resist layers with high aspect ratio features are described. The photosensitive layer is patterned exposed to actinic radiation and thereafter developed. For high aspect ratio patterns, the inventors have often observed a residue of resist material at the bottom of such features, and that this residue interferes with subsequent processing, such as filling the pattern with metal by a plating operation. To remove this residue, the patterned locations of the resist are exposed to a low dose of low-energy electron beam radiation, preferably having energy of less than 6 KeV and dosage of less than 200 .mu.C/cm.sup.2. After the electron beam exposure, the aperture is again exposed to a developer solution, which may be of the same composition as the developer initially used to develop the patterns.