Abstract: A system on a chip including a processor and an in-circuit emulator located within the processor. The processor is to perform processing functions associated with controlling operation of the system on a chip. The in-circuit emulator includes instrumentation logic to take over controlling the operation of the SOC from the processor, perform debugging and emulation functions, and output data including results of the debugging and emulation functions. A frame capture module is to package the data including the results of the debugging and emulation functions into frames having a parallel format. A serializer is to convert the frames from the parallel format to a serial format and output the frames having the serial format from the system on a chip.

Abstract: A hybrid circuit includes a system-in-a-package (SIP) and an integrated circuit. The SIP includes a solid-state memory, and a first control module. The first control module controls access to the solid-state memory based on a first control signal. The integrated circuit includes an embedded multi-media card (eMMC) module, a second control module, and a management module. The eMMC module is in communication with the SIP according to an eMMC standard. The first eMMC module transfers the first control signal to the first control module to access the solid-state memory. The second control module controls access to a magnetic storage device based on a second control signal. The management module generates the control signals to transfer first data between a host and the SIP via the eMMC module and transfer the first data or second data between the host and the magnetic storage device via the second control module.

Abstract: A serializer/deserializer for communicating with an integrated circuit. The serializer/deserializer includes a serializer configured to serialize, from a parallel format into a serial format, first data to be transferred from an external device to the integrated circuit. The external device is configured to perform testing on the integrated circuit. A deserializer is configured to deserialize, from the serial format into the parallel format, second data to be transferred from the integrated circuit to the external device. A test access port module is configured to receive, from a test interface arranged between the serializer/deserializer and the external device, third data for controlling the serializer and provide, to the test interface, fourth data associated with control of the test interface. The fourth data corresponds to the deserialization of the second data to be transferred from the integrated circuit to the external device.

Abstract: A system including a first first-in first-out (FIFO) module, a control module, and a second FIFO module. The first FIFO module is configured to receive, from a host, (i) a first block and (ii) a first logical block address corresponding to the first block, where the first block includes first data. The control module is configured to generate a second block, where the second block includes (i) the first data and (ii) the first logical block address. The second FIFO module is configured to receive a third block from the first FIFO module, where the third block includes a second logical block address, and to determine whether the third block is different than the first block depending on whether the second logical block address included in the third block is different than the first logical block address included in the second block.

Abstract: A storage device includes a wireless interface and a processor. The wireless interface is configured to receive wireless data from a device external to the storage device. The wireless data includes at least one data packet configured according to a wireless communication protocol. The processor is configured to receive the wireless data including the at least one data packet from the wireless interface, generate a storage device data package including the wireless data, store, in a storage region of the storage device, the storage device data package including the wireless data, retrieve the storage device data package from the storage region, recover the wireless data from the storage device data package, and provide the wireless data to the wireless interface for transmission to the device external to the storage device.

Abstract: A hard disk drive system including a controller and a plurality of slave testing modules located in respective components of the hard disk drive system. The controller is arranged on a printed circuit board of the hard disk drive system and is configured to transmit information from the hard disk drive system to a host device, receive information from the host device, and, using a master testing module located in the controller, provide test configuration data corresponding to the information received from the host device. Each of the plurality of slave testing modules is configured to receive the test configuration data from the master testing module and test operation of the respective component of the hard disk drive system using the test configuration data.

Abstract: A system for providing a test result from an integrated circuit to a status analyzer. A deserializer is configured to deserialize, into data frames, messages received from the integrated circuit. The messages include the test result and are received from the integrated circuit in a serial data format. A frame sync module is configured to synchronize the data frames, output the synchronized data frames, and generate a clock signal. A gateway module is configured to receive the synchronized data frames from the frame sync module in accordance with the clock signal, convert signal levels and signal timings associated with the synchronized data frames from a first format used by the frame sync module to a second format used by the status analyzer, and provide the synchronized data frames to the status analyzer in accordance with the signal levels and the signal timings in the second format used by the status analyzer.

Abstract: A hybrid circuit includes a system-in-a-package (SIP) and an integrated circuit. The SIP includes a solid-state memory, and a first control module. The first control module controls access to the solid-state memory based on a first control signal. The integrated circuit includes an embedded multi-media card (eMMC) module, a second control module, and a management module. The eMMC module is in communication with the SIP according to an eMMC standard. The first eMMC module transfers the first control signal to the first control module to access the solid-state memory. The second control module controls access to a magnetic storage device based on a second control signal. The management module generates the control signals to transfer first data between a host and the SIP via the eMMC module and transfer the first data or second data between the host and the magnetic storage device via the second control module.

Abstract: A hybrid control module includes a host interface control module configured to transfer data to and from a host interface. A first embedded multi-media card (eMMC) interface is configured to (i) connect to a second eMMC interface of a control module embedded solid-state memory (SSM) and (ii) transfer the data between the hybrid control module and the control module embedded SSM. A buffer management module is (i) in communication with the host interface control module, the first eMMC interface and a disk access control module and (ii) configured to buffer the data in volatile memory. The data is received by the buffer management module and from at least one of the host interface control module, the first eMMC interface, or the disk access control module.

Abstract: A system includes a management module transferring sectors between an interface or a memory and ports. The management module transfers a first portion of a first sector to or from a first port while transferring to or from a second port a second portion of the first sector or a first portion of a second sector. A first channel module reads from or writes to a first surface of a disk via a first head by transferring the first portion of the first sector to or from a first amplifier module. A second channel module, while the first channel module transfers the first portion of the first sector to or from the first amplifier module, reads from or writes to a second surface of the disk via a second head by transferring to or from a second amplifier module the second portion or the first portion of the second sector.

Abstract: A system includes a management module transferring sectors between an interface or a memory and ports. The management module transfers a first portion of a first sector to or from a first port while transferring to or from a second port a second portion of the first sector or a first portion of a second sector. A first channel module reads from or writes to a first surface of a disk via a first head by transferring the first portion of the first sector to or from a first amplifier module. A second channel module, while the first channel module transfers the first portion of the first sector to or from the first amplifier module, reads from or writes to a second surface of the disk via a second head by transferring to or from a second amplifier module the second portion or the first portion of the second sector.

Abstract: A printed circuit board of a hard disk drive system includes a first component and a plurality of second components of the hard disk drive system. The first component is configured to transmit information to, and receive information from, a host device via a communication interface of the printed circuit board. The first component includes a first testing module operating as a master testing module. Each of the plurality of second components includes a respective second testing module operating as a slave testing module. The first component is connected to each of the plurality of second components and is configured to provide test configuration data to each of the respective second testing modules. The test configuration data corresponds to the information received from the host device, and the test configuration data enables each of the respective second testing modules to test operation of the plurality of second components.

Abstract: A system including a frame capture module, a serializer, and a deserializer. The frame capture module is configured to receive, from a device under test, data corresponding to test results, and package the data into first data frames. The serializer is configured serialize the first data frames to form serial messages that include serialized data. The serializer includes i) a first serial link configured to output the serial messages according to a first clock domain, and ii) a second serial link configured to output the serial messages according to a second clock domain. The deserializer is configured to deserialize the serial messages received on the first serial link and the second serial link to form second data frames.

Abstract: A hard disk drive system includes a first channel module and a second channel module. The first channel module is configured to receive a first data from or transfer the first data to a first amplifier module of a hard disk assembly when reading from or writing to a first surface of a disk of the hard disk assembly. The second channel module is configured to receive a second data from or transfer the second data to a second amplifier module of the hard disk assembly when reading or writing to a second surface of the disk while the first channel module receives the first data from or transfers the first data to the first amplifier module.

Abstract: A system including a first buffer module, a first encoder module, a control module, and a second buffer module. The first buffer module receives (i) a first block and (ii) a first logical block address (LBA) for the first block from a host, where the first block includes first data. The first encoder module generates a first checksum based on (i) the first data and (ii) the first LBA. The control module generates a second block, where the second block includes (i) the first data, (ii) the first LBA, and (iii) the first checksum. The second buffer module receives a third block from the first buffer module, where the third block includes a second LBA. The second buffer module determines whether the third block is different than the first block depending on whether the second LBA in the third block is different than the first LBA in the second block.

Abstract: A system including an interface and a plurality of solder joint testing modules. The interface is configured to receive test configuration data to configure each of a plurality of integrated system test (IST) modules. Each of the plurality of solder joint testing modules is configured to, based on the test configuration data, i) apply a pulse having a predetermined amplitude and width to a solder joint associated with a respective one of the plurality of IST modules, ii) monitor a resultant waveform that is generated in response to the pulse, and iii) determine an integrity of the solder joint in response to the resultant waveform. Each of the plurality of solder joint testing modules and the respective ones of the plurality of IST modules are located on a same system on chip (SOC).

Abstract: A hard disk drive system includes a first channel module and a second channel module. The first channel module is configured to receive a first data from or transfer the first data to a first amplifier module of a hard disk assembly when reading from or writing to a first surface of a disk of the hard disk assembly. The second channel module is configured to receive a second data from or transfer the second data to a second amplifier module of the hard disk assembly when reading or writing to a second surface of the disk while the first channel module receives the first data from or transfers the first data to the first amplifier module.

Abstract: A hybrid control module includes a host interface control module configured to transfer data to and from a host interface. A first embedded multi-media card (eMMC) interface is configured to (i) connect to a second eMMC interface of a control module embedded solid-state memory (SSM) and (ii) transfer the data between the hybrid control module and the control module embedded SSM. A buffer management module is (i) in communication with the host interface control module, the first eMMC interface and a disk access control module and (ii) configured to buffer the data in volatile memory. The data is received by the buffer management module and from at least one of the host interface control module, the first eMMC interface, or the disk access control module.

Abstract: A hard disk drive system comprises an interface that receives test configuration data, that transmits test result data, and that transmits and receives application data. A system on chip (SOC) includes integrated system test (IST) modules. A memory module communicates with the SOC and includes memory and an IST module. One of the IST modules communicates with the interface and is a master IST module that receives the test configuration data and that configures others of the IST modules for testing a component of the hard disk drive system.

Abstract: A system includes a host first-in first-out (FIFO) module, a first encoder module, a control module, a disk FIFO module, and a second encoder module. The host FIFO module receives a block having data and selectively receives a host logical block address (HLBA). The first encoder module generates a first checksum based on the data and the HLBA and generates a first encoded block. The control module appends the HLBA to the first encoded block and generates an appended block. The disk FIFO module receives the block from the host FIFO module. The second encoder module selectively generates a second checksum based on the HLBA and the data in the block received by the disk FIFO module. The second encoder module compares the block received by the disk FIFO module to the block received by the host FIFO module based on the first and second checksums.