Patents by Inventor Son-Kwan Hwang
Son-Kwan Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220367364Abstract: A semiconductor package includes a first semiconductor chip, which includes a first semiconductor substrate and a first bonding layer on the first semiconductor substrate. A second semiconductor chip includes a second semiconductor substrate, a second bonding layer bonded to the first bonding layer, and a chip-through-via which penetrates the second semiconductor substrate and is connected to the second bonding layer. A passivation film extends along an upper side of the second semiconductor chip and does not extend along side-faces of the second semiconductor chip. The chip-through-via penetrates the passivation film. A multiple-gap-fill film extends along the upper side of the first semiconductor chip, the side faces of the second semiconductor chip, and the side faces of the passivation film. The multiple-gap-fill films includes an inorganic filling film and an organic filling film which are sequentially stacked on the first semiconductor chip.Type: ApplicationFiled: February 25, 2022Publication date: November 17, 2022Inventors: HYUNG JUN JEON, KWANG JIN MOON, SON-KWAN HWANG
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Patent number: 10777487Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer.Type: GrantFiled: September 14, 2018Date of Patent: September 15, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-il Choi, Kun-sang Park, Son-kwan Hwang, Ji-soon Park, Byung-lyul Park
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Publication number: 20190013260Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer.Type: ApplicationFiled: September 14, 2018Publication date: January 10, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Ju-il CHOI, Kun-sang PARK, Son-kwan HWANG, Ji-soon PARK, Byung-lyul PARK
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Patent number: 10128168Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer.Type: GrantFiled: November 17, 2014Date of Patent: November 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-il Choi, Kun-sang Park, Son-kwan Hwang, Ji-soon Park, Byung-lyul Park
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Publication number: 20180122721Abstract: A plug structure of a semiconductor chip includes a substrate, an insulating interlayer disposed on the substrate, wherein the insulating interlayer includes a pad structure disposed therein, a via hole penetrating the substrate and the insulating interlayer, wherein the via hole exposes the pad structure, an insulating pattern formed on an interior surface of the via hole, wherein the insulating pattern includes a burying portion, and the burying portion fills a notch disposed in the substrate at the interior surface of the via hole, and a plug formed on the insulating pattern within the via hole, wherein the plug is electrically connected with the pad structure.Type: ApplicationFiled: July 27, 2017Publication date: May 3, 2018Inventors: SON-KWAN HWANG, Ho-Jin LEE, Kwang-Jin MOON, Byung-Lyul PARK, Jin-Ho AN, Nae-In LEE
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Publication number: 20170345713Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.Type: ApplicationFiled: June 30, 2017Publication date: November 30, 2017Inventors: Jin-ho Chun, Byung-lyul PARK, Hyun-soo CHUNG, Gil-heyun CHOI, Son-kwan HWANG
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Patent number: 9698051Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.Type: GrantFiled: January 6, 2015Date of Patent: July 4, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-ho Chun, Byung-Iyul Park, Hyun-soo Chung, Gil-heyun Choi, Son-kwan Hwang
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Patent number: 9219035Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.Type: GrantFiled: January 13, 2014Date of Patent: December 22, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-jin Lee, Kang-wook Lee, Myeong-soon Park, Ju-il Choi, Son-kwan Hwang
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Publication number: 20150137387Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer.Type: ApplicationFiled: November 17, 2014Publication date: May 21, 2015Inventors: Ju-il CHOI, Kun-sang PARK, Son-kwan HWANG, Ji-soon PARK, Byung-lyul PARK
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Publication number: 20150111346Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.Type: ApplicationFiled: January 6, 2015Publication date: April 23, 2015Inventors: Jin-ho Chun, Byung-Iyul PARK, Hyun-soo CHUNG, Gil-heyun CHOI, Son-kwan HWANG
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Patent number: 8957526Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.Type: GrantFiled: January 4, 2013Date of Patent: February 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-ho Chun, Byung-lyul Park, Hyun-soo Chung, Gil-heyun Choi, Son-kwan Hwang
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Publication number: 20140329382Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a photoresist pattern having a side recess on a seed metal layer and forming a plating layer having a hem using a plating process to fill the side recess.Type: ApplicationFiled: November 14, 2013Publication date: November 6, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: SON-KWAN HWANG, JIN-HO CHUN, BYUNG-LYUL PARK, JEONG-GI JIN, GIL-HEYUN CHOI
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Publication number: 20140124901Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.Type: ApplicationFiled: January 13, 2014Publication date: May 8, 2014Inventors: Ho-jin Lee, Kang-wook Lee, Myeong-soon Park, Ju-iI Choi, Son-kwan Hwang
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Patent number: 8629059Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.Type: GrantFiled: December 16, 2010Date of Patent: January 14, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Jin Lee, Kang-Wook Lee, Myeong-Soon Park, Ju-il Choi, Son-Kwan Hwang
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Publication number: 20130313722Abstract: A semiconductor device includes an insulating layer on a surface of a substrate, a through-via structure vertically passing through the substrate and the insulating layer and being exposed on the insulating layer, and a via pad on a surface of the exposed through-via structure. The via pad includes a via pad body, and a via pad inlay below the via pad body and protruding into the insulating layer and surrounding the through-via structure. The via pad body and the via pad inlay include a via pad barrier layer directly on the insulating layer and a via pad metal layer on the via pad barrier layer.Type: ApplicationFiled: February 8, 2013Publication date: November 28, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Son-Kwan Hwang, Byung-Lyul Park, Hyun-Soo Chung, Jin-Ho Chun, Gil-Heyun Choi
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Patent number: 8564102Abstract: A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer.Type: GrantFiled: May 16, 2011Date of Patent: October 22, 2013Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Ju-il Choi, Jae-hyun Phee, Kyu-ha Lee, Ho-jin Lee, Son-kwan Hwang
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Publication number: 20130264720Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.Type: ApplicationFiled: January 4, 2013Publication date: October 10, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Jin-ho Chun, Byung-lyul Park, Hyun-soo Chung, Gil-heyun Choi, Son-kwan Hwang
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Patent number: 8513802Abstract: A semiconductor device having semiconductor chips of different thicknesses is provided. The semiconductor device may include a first semiconductor chip, a sub-board on a first side of the first semiconductor chip, at least one second semiconductor chip on a second side of the first semiconductor chip, at least one external contact terminal on the at least one second semiconductor chip. In example embodiments the at least one second semiconductor chip may include a plurality of through silicon vias and the at least one external contact terminal may be in electrical contact with the first semiconductor chip and the at least one second semiconductor chip via the plurality of through silicon vias. In example embodiments, the at least one second semiconductor chip may be thinner than the first semiconductor chip.Type: GrantFiled: January 25, 2011Date of Patent: August 20, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Keum-Hee Ma, Woo-Dong Lee, Min-Seung Yoon, Ju-Il Choi, Sang-Sick Park, Son-Kwan Hwang
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Patent number: 8482129Abstract: A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.Type: GrantFiled: February 15, 2011Date of Patent: July 9, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: In-Young Lee, Ho-Jin Lee, Hyun-Soo Chung, Ju-Il Choi, Son-Kwan Hwang
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Patent number: 8415804Abstract: A semiconductor chip, a method of fabricating the same, and a stack module and a memory card including the semiconductor chip include a first surface and a second surface facing the first surface is provided. At least one via hole including a first portion extending in a direction from the first surface of the substrate to the second surface of the substrate and a second portion that is connected to the first portion and has a tapered shape. At least one via electrode filling the at least one via hole is provided.Type: GrantFiled: December 16, 2009Date of Patent: April 9, 2013Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Ho-jin Lee, Dong-hyun Jang, In-young Lee, Min-seung Yoon, Son-kwan Hwang