Patents by Inventor Soon-Cheon Seo

Soon-Cheon Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190259939
    Abstract: Methods for MTJ patterning for a MTJ device are provided. For example, a method includes (a) providing an MTJ device comprising a substrate comprising a plurality of bottom electrodes, a MTJ layer disposed on the substrate, and a plurality of pillars disposed on the MTJ layer and over the plurality of bottom electrodes, wherein the plurality of pillars comprise a metal layer and a hard mask layer disposed on the metal layer, (b) conducting a first ion beam etching of the MTJ device; (c) rotating the MTJ device by 90 degrees in a clockwise or a counter clockwise direction about an axis perpendicular to a top surface of the MTJ device from a starting position; (d) conducting a second ion beam etching of the MTJ device; and (e) repeating steps (c) and (d).
    Type: Application
    Filed: February 20, 2018
    Publication date: August 22, 2019
    Inventors: SOON-CHEON SEO, Kisup Chung, Injo OK, Seyoung Kim, Choonghyun Lee
  • Patent number: 10381462
    Abstract: A stacked nanowire field effect transistor (FET) including a plurality of vertically stacked nanowire channels. Each nanowire channel is vertically separated from one another by sacrificial segment. A gate stack is on the upper surface of the semiconductor substrate. The gate stack includes a conductive element that wraps around the nanowire channels. Source/drain regions are on the upper surface of the semiconductor substrate. The source/drain regions directly contact the ends of the nanowire channel. The stacked nanowire FET further includes nanowire channel spacers that encapsulate the ends of the nanowire channel such that the source/drain regions are separated from the gate stack.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Soon-Cheon Seo
  • Patent number: 10381074
    Abstract: A resistive processing unit includes an analog memory element coupled to a read row line and a read column line, a first current subtraction field-effect transistor (FET) coupled to the read row line and the analog memory element, and a second current subtraction FET coupled to the read column line and the analog memory element. The analog memory element is configured to store a weight value as its conductance. Application of a gate pulse voltage to one of the first current subtraction FET and the second current subtraction FET during application of a read pulse voltage to one of the read row line and the read column line reduces a measured conductance of the analog memory element, and the reduction of the measured conductance of the analog memory element provides net current for the stored weight value.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Seyoung Kim, Soon-Cheon Seo, Injo Ok, Choonghyun Lee
  • Patent number: 10374066
    Abstract: A semiconductor structure and a method for fabricating the same. The structure includes a substrate, active fin structures, and non-active fin structures. The structure further includes isolation regions in contact with the active fin structures, and isolation regions in contact with the non-active fin structures. A first gate structure is in contact with the active fin structures and the isolation regions that are in contact with the active fin structures. A second gate structure is in contact with the non-active fin structures. The method includes forming an isolation region between fin structures. A mask is formed over active fin structures and dummy fin structures are then removed to form a plurality of trenches between the isolation regions. A nitride-based layer is formed in contact with isolation regions corresponding to the dummy fin structures. The nitride-based layer forms a non-active fin structure within each trench of the trenches.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventor: Soon-Cheon Seo
  • Publication number: 20190229200
    Abstract: A method of forming a plurality of vertical fin field effect transistors is provided. The method includes forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate, forming an isolation region between the first region and the second region, forming a gate dielectric layer on the vertical fins, forming a first work function layer on the gate dielectric layer, removing an upper portion of the first work function layer from the vertical fin on the first region and the vertical fin on the second region, and forming a second work function layer on the first work function layer and the exposed upper portion of the gate dielectric layer, wherein the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.
    Type: Application
    Filed: March 22, 2019
    Publication date: July 25, 2019
    Inventors: Choonghyun Lee, Brent A. Anderson, Injo Ok, Soon-Cheon Seo
  • Patent number: 10361203
    Abstract: A semiconductor structure includes a first layered dipole structure formed within a gate trench within a first polarity region of the semiconductor structure. A second layered dipole structure is formed within a gate trench within a second polarity region of the semiconductor structure and formed upon the first layered dipole structure. The layered dipole structure nearest to the bottom of the gate trench includes a dipole layer of opposite polarity relative to the polarity region of the semiconductor structure where the gate trench is located and reduces source to drain leakage.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. V. S. Surisetty
  • Patent number: 10355109
    Abstract: A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel region of the fin and forming a second sacrificial gate stack over a second channel region of the fin, forming spacers adjacent to the first sacrificial gate stack and the second sacrificial gate stack, depositing a first liner layer on the spacers, the first sacrificial gate stack and the second sacrificial gate stack, depositing a first sacrificial layer on the first liner layer, removing a portion of the first sacrificial layer over the first gate stack to expose a portion of the first liner layer on the first sacrificial gate stack, and growing a first semiconductor material on exposed portions of the fin to form a first source/drain region adjacent to the first gate sacrificial gate stack.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thamarai Selvi Devarajan, Sanjay C. Mehta, Eric R. Miller, Soon-Cheon Seo
  • Patent number: 10355080
    Abstract: A semiconductor structure including one or more semiconductor devices on a wafer. The one or more devices having source/drain junctions. The semiconductor structure further includes a recessed middle-of-line (MOL) oxide layer, and an air-gap oxide layer including one or more introduced air-gaps. The air-gap oxide layer is positioned over the one or more semiconductor devices and the MOL oxide layer. A nitride layer is positioned over the one or more semiconductor devices. Trenches are formed through the nitride layer down to the source/drain junctions. A silicide fills the trenches.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. V. S. Surisetty
  • Publication number: 20190214314
    Abstract: Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Inventors: Soon-Cheon Seo, Choonghyun Lee, Injo Ok
  • Publication number: 20190214389
    Abstract: A method for making a semiconductor includes patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor, and etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process.
    Type: Application
    Filed: March 18, 2019
    Publication date: July 11, 2019
    Inventor: Soon-Cheon Seo
  • Patent number: 10347739
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Soon-Cheon Seo, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10347456
    Abstract: A method is presented for controlling an electric field from a gate structure. The method includes forming a hardmask over a fin stack including a plurality of layers, forming a first dielectric layer over the hardmask, forming a sacrificial layer over the first dielectric layer, etching the sacrificial layer to expose a top surface of the first dielectric layer, depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer, removing a layer of the plurality of layers of the fin stack to define an air gap within the fin stack, and forming triangle-shaped epitaxial growths within the air gap defined within the fin stack.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim
  • Patent number: 10347632
    Abstract: The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. V. S. Surisetty
  • Patent number: 10347633
    Abstract: The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. V. S. Surisetty
  • Patent number: 10325820
    Abstract: Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Soon-Cheon Seo, Choonghyun Lee, Injo Ok
  • Publication number: 20190181236
    Abstract: A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 13, 2019
    Inventors: Choonghyun Lee, Seyoung Kim, Injo Ok, Soon-Cheon Seo
  • Patent number: 10319721
    Abstract: Aspects of the disclosure include a method for making a semiconductor, including patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor. The method also includes etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Soon-Cheon Seo
  • Publication number: 20190172830
    Abstract: Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 6, 2019
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo, Seyoung Kim
  • Publication number: 20190165128
    Abstract: A method of manufacturing a bipolar junction transistor (BJT) structure is provided. Pattern etching through a second semiconductor layer and recessing a silicon germanium layer are performed to form a plurality of vertical fins each including a silicon germanium pattern, a second semiconductor pattern and a hard mask pattern sequentially stacked on a first semiconductor layer above a substrate. First spacers are formed on sidewalls of the plurality of vertical fins. Exposed silicon germanium layer above the first semiconductor layer is directionally etched away. A germanium oxide layer is conformally coated to cover all exposed top and sidewall surfaces. Condensation annealing followed by silicon oxide strip is performed. The first spacers, remaining germanium oxide layer and the hard mask pattern are removed. A dielectric material is deposited to isolate the plurality of vertical fins.
    Type: Application
    Filed: August 10, 2018
    Publication date: May 30, 2019
    Inventors: SEYOUNG KIM, CHOONGHYUN LEE, INJO OK, SOON-CHEON SEO
  • Publication number: 20190157388
    Abstract: A method of forming a semiconductor structure includes forming a middle-of-line (MOL) oxide layer in the semiconductor structure. The MOL oxide layer including multiple gate stacks formed on a substrate. A nitride layer is formed over a silicide in the MOL oxide layer. At least one self-aligned contact area (CA) element is formed within the nitride layer. The MOL oxide layer is selectively recessed on a first side and a second side of the at least one self-aligned CA element leaving remaining portions of the MOL oxide layer on the nitride layer and a nitride. A nitride cap of the plurality of gate stacks is selectively recessed. An air-gap oxide layer is deposited for introducing one or more air-gaps in the deposited air-gap oxide layer. The air gap oxide layer is reduced to the at least one self-aligned CA element and the nitride layer.
    Type: Application
    Filed: January 29, 2019
    Publication date: May 23, 2019
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V.V.S. Surisetty