Patents by Inventor Soon-Moon Jung

Soon-Moon Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8004885
    Abstract: A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A well of an unselected layer is biased with a second well voltage higher than the first well voltage.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: August 23, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-In Yun, Jae-Hoon Jang, Soon-Moon Jung, Han-Soo Kim, Jun-Beom Park, Jae-Hun Jeong
  • Patent number: 7982221
    Abstract: A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: July 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gong-Heum Han, Hyou-Youn Nam, Bo-Tak Lim, Han-Byung Park, Soon-Moon Jung, Hoon Lim
  • Publication number: 20110171787
    Abstract: In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region.
    Type: Application
    Filed: March 23, 2011
    Publication date: July 14, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jonghyuk Kim, Han-Soo Kim, YoungSeop Rah, Min-sung Song, Jang Young Chul, Soon-Moon Jung, Wonseok Cho
  • Patent number: 7978561
    Abstract: Provided is a semiconductor device having transistors of stacked structure. The semiconductor memory device having transistors includes a memory cell array block which includes a plurality of word lines and a plurality of memory cells which each includes at least one first transistor connected between the plurality of word lines, and a word line decoder which includes a plurality of drivers which drive the plurality of word lines, respectively, wherein a plurality of word lines are disposed on a first layer, and a plurality of drivers are disposed on at least two second layers.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: July 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Byung Park, Soon-Moon Jung, Hoon Lim
  • Publication number: 20110163411
    Abstract: A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.
    Type: Application
    Filed: March 16, 2011
    Publication date: July 7, 2011
    Inventors: Young-Chul Jang, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • Patent number: 7960844
    Abstract: Disclosed are a flash memory device and method of operation. The flash memory device includes a bottom memory cell array and a top memory cell array disposed over the bottom memory cell array. The bottom memory cell array includes a bottom semiconductor layer, a bottom well, and a plurality of bottom memory cell units. The top memory cell array includes a top semiconductor layer, a top well, and a plurality of top memory cell units. A well bias line is disposed over the top memory cell array and includes a bottom well bias line and a top well bias line, The bottom well bias line is electrically connected to the bottom well, and the top well bias line is electrically connected to the top well.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: June 14, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Chul Jang, Han-Soo Kim, Jae-Hun Jeong, Soon-Moon Jung
  • Patent number: 7936002
    Abstract: In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: May 3, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jonghyuk Kim, Han-Soo Kim, YoungSeop Rah, Min-sung Song, Jang Young Chul, Soon-Moon Jung, Wonseok Cho
  • Patent number: 7927932
    Abstract: A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: April 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Byung Park, Soon-Moon Jung, Hoon Lim, Cha-Dong Yeo, Byoung-Keun Son, Jae-Joo Shim, Chang-Min Hong
  • Patent number: 7910433
    Abstract: A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: March 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Chul Jang, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • Publication number: 20110014754
    Abstract: A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line.
    Type: Application
    Filed: September 23, 2010
    Publication date: January 20, 2011
    Inventors: Han-Byung Park, Soon-Moon Jung, Hoon Lim, Cha-Dong Yeo, Byoung-Keun Son, Jae-Joo Shim, Chang-Min Hong
  • Publication number: 20100330752
    Abstract: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.
    Type: Application
    Filed: July 23, 2010
    Publication date: December 30, 2010
    Inventors: Jae-Hun Jeong, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • Patent number: 7825472
    Abstract: A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: November 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Byung Park, Soon-Moon Jung, Hoon Lim, Cha-Dong Yeo, Byoung-Keun Son, Jae-Joo Shim, Chang-Min Hong
  • Publication number: 20100240209
    Abstract: Provided are semiconductor devices and methods of forming the same. The semiconductor devices include a substrate further including a hydrogen implantation layer and a gate structure formed on the hydrogen implantation layer to include a first insulating layer, a charge storage layer, a second insulating layer and a conductive layer.
    Type: Application
    Filed: June 3, 2010
    Publication date: September 23, 2010
    Inventors: Jae-Hun Jeong, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • Patent number: 7795651
    Abstract: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: September 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hun Jeong, Ki-Nam Kim, Soon-Moon Jung, Jae-Hoon Jang
  • Patent number: 7719033
    Abstract: Semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same are provided. The semiconductor devices include a semiconductor substrate and a lower interlayer insulating layer disposed on the semiconductor substrate. A lower semiconductor body disposed on or in the lower interlayer insulating layer. A lower TFT includes a lower source region and a lower drain region, which are disposed in the lower semiconductor body, and a lower gate electrode, which covers and crosses at least portions of at least two surfaces of the lower semiconductor body disposed between the lower source and drain regions.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: May 18, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hun Jeong, Soon-Moon Jung, Hoon Lim, Won-Seok Cho, Jin-Ho Kim, Chang-Min Hong, Jong-Hyuk Kim, Kun-Ho Kwak
  • Publication number: 20100120217
    Abstract: An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.
    Type: Application
    Filed: January 14, 2010
    Publication date: May 13, 2010
    Inventors: Jae-Hoon Jang, Soon-Moon Jung, Young-Seop Rah, Han-Byung Park
  • Publication number: 20100118606
    Abstract: In a method of programming a non-volatile memory device, and in a device incorporating the same, the memory device includes: a plurality of memory cell transistors arranged in a plurality of transistor strings, wherein a transistor string includes a plurality of memory cell transistors arranged in series; a plurality of word lines, each word line connected to a corresponding memory cell transistor of each of the different transistor strings; and a plurality of bit lines, each bit line connected to one of the transistor strings.
    Type: Application
    Filed: November 12, 2009
    Publication date: May 13, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae Duk Lee, Soon Moon Jung, Jung Dal Choi
  • Patent number: 7709323
    Abstract: Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line patte
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoo-Sung Cho, Soon-Moon Jung, Won-Seok Cho, Jong-Hyuk Kim, Jae-Hun Jeong, Jae-Hoon Jang
  • Patent number: 7701771
    Abstract: A memory device may include L semiconductor layers, a gate structure on each of the semiconductor layers, N bitlines, and/or a common source line on each of the semiconductor layers. The L semiconductor layers may be stacked, and/or L may be an integer greater than 1. The N bitlines may be on the gate structures and crossing over the gate structures, and/or N may be an integer greater than 1. Each of the common source lines may be connected to each other such that the common source lines have equipotentiality with each other.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: April 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hun Jeong, Ki-Nam Kim, Soon-Moon Jung, Hoo-Sung Cho
  • Patent number: 7683404
    Abstract: A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the memory cell array.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: March 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Chul Jang, Won-Seok Cho, Jae-Hoon Jang, Soon-Moon Jung, Hoo-Sung Cho, Jong-Hyuk Kim