Patents by Inventor Sotirios Athanasiou
Sotirios Athanasiou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11380766Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.Type: GrantFiled: June 7, 2019Date of Patent: July 5, 2022Assignee: STMicroelectronics SAInventors: Sotirios Athanasiou, Philippe Galy
-
Publication number: 20210317559Abstract: A method of forming an oxide layer in an in-situ steam generation (ISSG) process, including providing a silicon substrate in a rapid thermal process (RTP) chamber and injecting a gas mixture into the RTP chamber. The method further includes heating a surface of the silicon substrate to a reaction temperature, so that the gas mixture reacts close to the surface to form steam and thereby oxidize the silicon substrate to form the oxide layer on the surface, and wherein the gas mixture comprises hydrogen (H2), oxygen (O2) and nitrous oxide (N2O).Type: ApplicationFiled: April 12, 2021Publication date: October 14, 2021Applicant: X-FAB France SASInventors: Sotirios ATHANASIOU, Laurence VALLIER
-
Publication number: 20210234024Abstract: A method of manufacturing of a semiconductor device, comprising: providing a semiconductor substrate having a first region, a second region and a third region; on the first region, providing a first thin dielectric layer; on the second region, providing a second thick dielectric layer; on the third region, providing an ONO stack; on each of the first, second and third regions, providing at least one gate structure; performing an oxidation step so as to form an oxide layer on each of the gate structures of the first, second and third regions and exposed portions of the first and second dielectric layers; providing a first tetraethyl orthosilicate, TEOS, layer across the second and third regions; blanket depositing a first silicon nitride, SiN, layer across the first, second and third regions; and etching the first SiN layer leaving at least some of said first SiN layer on each gate structure of the first, second and third regions so as to form a first SiN sidewall spacer portion on each gate structure of the fType: ApplicationFiled: January 27, 2021Publication date: July 29, 2021Inventors: Sébastien Daveau, Sotirios Athanasiou
-
Publication number: 20190288079Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.Type: ApplicationFiled: June 7, 2019Publication date: September 19, 2019Applicant: STMicroelectronics SAInventors: Sotirios ATHANASIOU, Philippe GALY
-
Patent number: 10367068Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.Type: GrantFiled: February 8, 2017Date of Patent: July 30, 2019Assignee: STMicroelectronics SAAInventors: Sotirios Athanasiou, Philippe Galy
-
Patent number: 10211201Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.Type: GrantFiled: March 7, 2018Date of Patent: February 19, 2019Assignee: STMicroelectronics SAInventors: Philippe Galy, Sotirios Athanasiou
-
Patent number: 10128242Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.Type: GrantFiled: November 6, 2017Date of Patent: November 13, 2018Assignee: STMicroelectronics SAInventors: Philippe Galy, Sotirios Athanasiou
-
Patent number: 10096708Abstract: An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.Type: GrantFiled: August 8, 2016Date of Patent: October 9, 2018Assignee: STMicroelectronics SAInventors: Sotirios Athanasiou, Philippe Galy
-
Publication number: 20180197848Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.Type: ApplicationFiled: March 7, 2018Publication date: July 12, 2018Applicant: STMicroelectronics SAInventors: Philippe Galy, Sotirios Athanasiou
-
Patent number: 9947650Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.Type: GrantFiled: April 26, 2017Date of Patent: April 17, 2018Assignee: STMicroelectronics SAInventors: Philippe Galy, Sotirios Athanasiou
-
Publication number: 20180102358Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.Type: ApplicationFiled: April 26, 2017Publication date: April 12, 2018Applicant: STMicroelectronics SAInventors: Philippe Galy, Sotirios Athanasiou
-
Publication number: 20180061833Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.Type: ApplicationFiled: November 6, 2017Publication date: March 1, 2018Applicant: STMicroelectronics SAInventors: Philippe Galy, Sotirios Athanasiou
-
Publication number: 20180012965Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.Type: ApplicationFiled: February 8, 2017Publication date: January 11, 2018Applicant: STMicroelectronics SAInventors: Sotirios Athanasiou, Philippe Galy
-
Patent number: 9837413Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.Type: GrantFiled: February 11, 2016Date of Patent: December 5, 2017Assignee: STMicroelectronics SAInventors: Philippe Galy, Sotirios Athanasiou
-
Patent number: 9831288Abstract: The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel zone (203) arranged between the first and second conduction electrodes; a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222); an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.Type: GrantFiled: December 22, 2016Date of Patent: November 28, 2017Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Laurent Grenouillet, Sotirios Athanasiou, Philippe Galy
-
Publication number: 20170288059Abstract: An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.Type: ApplicationFiled: August 8, 2016Publication date: October 5, 2017Applicant: STMicroelectronics SAInventors: Sotirios Athanasiou, Philippe Galy
-
Patent number: 9746863Abstract: An electronic device includes an integrated circuit with a MOS transistor and a heating circuit electrically coupled to at least two points of one of the source or drain semiconductive region of the transistor. A portion of the source or drain semiconductive region between the two points forms a resistive element. The heating circuit is configured to cause a current to circulate through the resistive element between the two points to heat an active region of the transistor.Type: GrantFiled: December 4, 2015Date of Patent: August 29, 2017Assignee: STMicroelectronics SAInventors: Philippe Galy, Sotirios Athanasiou, Julien Le Coz, Sylvain Engels
-
Publication number: 20170179196Abstract: The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel zone (203) arranged between the first and second conduction electrodes; a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222); an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.Type: ApplicationFiled: December 22, 2016Publication date: June 22, 2017Applicants: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SAInventors: Laurent GRENOUILLET, Sotirios Athanasiou, Philippe Galy
-
Publication number: 20170012043Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.Type: ApplicationFiled: February 11, 2016Publication date: January 12, 2017Applicant: STMicroelectronics SAInventors: Philippe Galy, Sotirios Athanasiou
-
Publication number: 20160370815Abstract: An electronic device includes an integrated circuit with a MOS transistor and a heating circuit electrically coupled to at least two points of one of the source or drain semiconductive region of the transistor. A portion of the source or drain semiconductive region between the two points forms a resistive element. The heating circuit is configured to cause a current to circulate through the resistive element between the two points to heat an active region of the transistor.Type: ApplicationFiled: December 4, 2015Publication date: December 22, 2016Applicant: STMicroelectronics SAInventors: Philippe Galy, Sotirios Athanasiou, Julien Le Coz, Sylvain Engels