Patents by Inventor Sotirios Athanasiou

Sotirios Athanasiou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190288079
    Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 19, 2019
    Applicant: STMicroelectronics SA
    Inventors: Sotirios ATHANASIOU, Philippe GALY
  • Patent number: 10367068
    Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: July 30, 2019
    Assignee: STMicroelectronics SAA
    Inventors: Sotirios Athanasiou, Philippe Galy
  • Patent number: 10211201
    Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Patent number: 10128242
    Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: November 13, 2018
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Patent number: 10096708
    Abstract: An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 9, 2018
    Assignee: STMicroelectronics SA
    Inventors: Sotirios Athanasiou, Philippe Galy
  • Publication number: 20180197848
    Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.
    Type: Application
    Filed: March 7, 2018
    Publication date: July 12, 2018
    Applicant: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Patent number: 9947650
    Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: April 17, 2018
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Publication number: 20180102358
    Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.
    Type: Application
    Filed: April 26, 2017
    Publication date: April 12, 2018
    Applicant: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Publication number: 20180061833
    Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.
    Type: Application
    Filed: November 6, 2017
    Publication date: March 1, 2018
    Applicant: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Publication number: 20180012965
    Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.
    Type: Application
    Filed: February 8, 2017
    Publication date: January 11, 2018
    Applicant: STMicroelectronics SA
    Inventors: Sotirios Athanasiou, Philippe Galy
  • Patent number: 9837413
    Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: December 5, 2017
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Patent number: 9831288
    Abstract: The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel zone (203) arranged between the first and second conduction electrodes; a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222); an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: November 28, 2017
    Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Laurent Grenouillet, Sotirios Athanasiou, Philippe Galy
  • Publication number: 20170288059
    Abstract: An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.
    Type: Application
    Filed: August 8, 2016
    Publication date: October 5, 2017
    Applicant: STMicroelectronics SA
    Inventors: Sotirios Athanasiou, Philippe Galy
  • Patent number: 9746863
    Abstract: An electronic device includes an integrated circuit with a MOS transistor and a heating circuit electrically coupled to at least two points of one of the source or drain semiconductive region of the transistor. A portion of the source or drain semiconductive region between the two points forms a resistive element. The heating circuit is configured to cause a current to circulate through the resistive element between the two points to heat an active region of the transistor.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: August 29, 2017
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou, Julien Le Coz, Sylvain Engels
  • Publication number: 20170179196
    Abstract: The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel zone (203) arranged between the first and second conduction electrodes; a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222); an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 22, 2017
    Applicants: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SA
    Inventors: Laurent GRENOUILLET, Sotirios Athanasiou, Philippe Galy
  • Publication number: 20170012043
    Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.
    Type: Application
    Filed: February 11, 2016
    Publication date: January 12, 2017
    Applicant: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou
  • Publication number: 20160370815
    Abstract: An electronic device includes an integrated circuit with a MOS transistor and a heating circuit electrically coupled to at least two points of one of the source or drain semiconductive region of the transistor. A portion of the source or drain semiconductive region between the two points forms a resistive element. The heating circuit is configured to cause a current to circulate through the resistive element between the two points to heat an active region of the transistor.
    Type: Application
    Filed: December 4, 2015
    Publication date: December 22, 2016
    Applicant: STMicroelectronics SA
    Inventors: Philippe Galy, Sotirios Athanasiou, Julien Le Coz, Sylvain Engels