Patents by Inventor Spyridon Skordas

Spyridon Skordas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190164163
    Abstract: Devices and methods for granting requests for authorization using data of devices associated with requestors are disclosed. A method includes: receiving, by a computing device, a request for authorization; receiving, by the computing device, identification information for at least one device of a requestor; determining, by the computing device, a risk score using the received identification information for the at least one device of the requestor; and in response to the risk score exceeding a predetermined threshold, the computing device granting the request for authorization.
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventors: Spyridon SKORDAS, Lawrence A. CLEVENGER, Richard C. JOHNSON
  • Patent number: 10269760
    Abstract: A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips, where the first chips are on a first substrate; forming a second bonding layer on a second wafer and second chips, where the second chips are on a second substrate; separating the second chips from the second wafer, wherein a portion of the second bonding layer remains on the second chips; moving the separated second chips to a cleaning chamber using a vacuum chuck; cleaning the separated second chips in the cleaning chamber; and bonding the second bonding layer on the separated second chips to the first bonding layer on the first chips.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Spyridon Skordas
  • Patent number: 10211178
    Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
  • Patent number: 10170447
    Abstract: A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips, where the first chips are on a first substrate; forming a second bonding layer on a second wafer and second chips, where the second chips are on a second substrate; separating the second chips from the second wafer, wherein a portion of the second bonding layer remains on the second chips; moving the separated second chips to a cleaning chamber using a vacuum chuck; cleaning the separated second chips in the cleaning chamber; and bonding the second bonding layer on the separated second chips to the first bonding layer on the first chips.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Spyridon Skordas
  • Patent number: 10157757
    Abstract: A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Spyridon Skordas, Robert R. Young, Jr.
  • Publication number: 20180350639
    Abstract: A wafer bonding method includes placing a first wafer on a first bonding framework including a plurality of outlet holes around a periphery of the first bonding framework. A second wafer is placed on a second bonding framework that includes a plurality of inlet holes around a periphery of the second bonding framework. The first bonding framework is in overlapping relation to the second bonding framework such that a gap exist between the first wafer and the second wafer. A gas stream is circulated through the gap between the first wafer and the second wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the first wafer and the second wafer.
    Type: Application
    Filed: July 23, 2018
    Publication date: December 6, 2018
    Inventors: Wei Lin, Spyridon Skordas, Robert R. Young, JR.
  • Publication number: 20180351596
    Abstract: A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.
    Type: Application
    Filed: May 30, 2017
    Publication date: December 6, 2018
    Inventors: Maryam Ashoori, Benjamin D. Briggs, Justin A. Canaperi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo, Spyridon Skordas
  • Patent number: 10134577
    Abstract: Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: November 20, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Richard F. Indyk, Deepika Priyadarshini, Spyridon Skordas, Edmund J. Sprogis, Anthony K. Stamper, Kevin R. Winstel
  • Patent number: 10056272
    Abstract: A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Spyridon Skordas, Robert R. Young, Jr.
  • Publication number: 20180226374
    Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
    Type: Application
    Filed: April 5, 2018
    Publication date: August 9, 2018
    Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
  • Patent number: 10020279
    Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: July 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
  • Publication number: 20180082863
    Abstract: A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 22, 2018
    Inventors: Wei Lin, Spyridon Skordas, Robert R. Young, JR.
  • Publication number: 20180082864
    Abstract: A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.
    Type: Application
    Filed: November 27, 2017
    Publication date: March 22, 2018
    Inventors: Wei Lin, Spyridon Skordas, Robert R. Young, JR.
  • Patent number: 9922851
    Abstract: A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Spyridon Skordas, Robert R. Young, Jr.
  • Publication number: 20180076170
    Abstract: A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips, where the first chips are on a first substrate; forming a second bonding layer on a second wafer and second chips, where the second chips are on a second substrate; separating the second chips from the second wafer, wherein a portion of the second bonding layer remains on the second chips; moving the separated second chips to a cleaning chamber using a vacuum chuck; cleaning the separated second chips in the cleaning chamber; and bonding the second bonding layer on the separated second chips to the first bonding layer on the first chips.
    Type: Application
    Filed: November 17, 2017
    Publication date: March 15, 2018
    Inventors: Wei Lin, Spyridon Skordas
  • Publication number: 20180068974
    Abstract: A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips, where the first chips are on a first substrate; forming a second bonding layer on a second wafer and second chips, where the second chips are on a second substrate; separating the second chips from the second wafer, wherein a portion of the second bonding layer remains on the second chips; moving the separated second chips to a cleaning chamber using a vacuum chuck; cleaning the separated second chips in the cleaning chamber; and bonding the second bonding layer on the separated second chips to the first bonding layer on the first chips.
    Type: Application
    Filed: November 17, 2017
    Publication date: March 8, 2018
    Inventors: Wei Lin, Spyridon Skordas
  • Patent number: 9881896
    Abstract: A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips, where the first chips are on a first substrate; forming a second bonding layer on a second wafer and second chips, where the second chips are on a second substrate; separating the second chips from the second wafer, wherein a portion of the second bonding layer remains on the second chips; moving the separated second chips to a cleaning chamber using a vacuum chuck; cleaning the separated second chips in the cleaning chamber; and bonding the second bonding layer on the separated second chips to the first bonding layer on the first chips.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Spyridon Skordas
  • Patent number: 9784917
    Abstract: Embodiments are directed to a coupler system having an interposer configured to couple optical signals. The interposer includes at least one optoelectronic component formed on a glass substrate. The interposer further includes at least one waveguide formed on the glass substrate and configured to couple the optical signals to or from the at least one optoelectronic component, wherein the at least one waveguide comprises a waveguide material having grain diameters greater than about one micron and an optical loss less than about one decibel per centimeter of optical propagation.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Stephen M. Gates, Joyeeta Nag, Jason S. Orcutt, Jean-Olivier Plouchart, Spyridon Skordas
  • Publication number: 20170221850
    Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
    Type: Application
    Filed: April 19, 2017
    Publication date: August 3, 2017
    Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
  • Publication number: 20170179077
    Abstract: A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips, where the first chips are on a first substrate; forming a second bonding layer on a second wafer and second chips, where the second chips are on a second substrate; separating the second chips from the second wafer, wherein a portion of the second bonding layer remains on the second chips; moving the separated second chips to a cleaning chamber using a vacuum chuck; cleaning the separated second chips in the cleaning chamber; and bonding the second bonding layer on the separated second chips to the first bonding layer on the first chips.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Inventors: Wei Lin, Spyridon Skordas