Patents by Inventor SRAVANI KONDA

SRAVANI KONDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Detection of shellcode
    Patent number: 10803165
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to monitor code as it executes. The code can include self-modifying code. The system can log an event if the self-modifying code occurred in a GetPC address region.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: October 13, 2020
    Assignee: McAfee, LLC
    Inventors: Koichi Yamada, Palanivel Rajan Shanmugavelayutham, Greg W. Dalcher, Sravani Konda
  • Techniques for enforcing control flow integrity using binary translation
    Patent number: 10268819
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine a valid target address for a branch instruction from information stored in a relocation table, a linkage table, or both, the relocation table and the linkage table associated with a binary file and store the valid target address in a table in memory, the valid target address to validate a target address for a translated portion of a routine of the binary file.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: April 23, 2019
    Assignee: INTEL CORPORATION
    Inventors: Koichi Yamada, Palanivelrajan Shanmugavelayutham, Sravani Konda
  • TECHNIQUES FOR ENFORCING CONTROL FLOW INTEGRITY USING BINARY TRANSLATION
    Publication number: 20170316201
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine a valid target address for a branch instruction from information stored in a relocation table, a linkage table, or both, the relocation table and the linkage table associated with a binary file and store the valid target address in a table in memory, the valid target address to validate a target address for a translated portion of a routine of the binary file.
    Type: Application
    Filed: February 13, 2017
    Publication date: November 2, 2017
    Applicant: INTEL CORPORATION
    Inventors: KOICHI YAMADA, PALANIVELRAJAN SHANMUGAVELAYUTHAM, SRAVANI KONDA
  • Techniques for enforcing control flow integrity using binary translation
    Patent number: 9569613
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine a valid target address for a branch instruction from information stored in a relocation table, a linkage table, or both, the relocation table and the linkage table associated with a binary file and store the valid target address in a table in memory, the valid target address to validate a target address for a translated portion of a routine of the binary file.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: February 14, 2017
    Assignee: INTEL CORPORATION
    Inventors: Koichi Yamada, Palanivelrajan Shanmugavelayutham, Sravani Konda
  • DETECTION OF SHELLCODE
    Publication number: 20160381043
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to monitor code as it executes. The code can include self-modifying code. The system can log an event if the self-modifying code occurred in a GetPC address region.
    Type: Application
    Filed: September 26, 2015
    Publication date: December 29, 2016
    Applicant: McAfee, Inc.
    Inventors: Koichi Yamada, Palanivel Rajan Shanmugavelayutham, Greg W. Dalcher, Sravani Konda
  • TECHNIQUES FOR ENFORCING CONTROL FLOW INTEGRITY USING BINARY TRANSLATION
    Publication number: 20160179546
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine a valid target address for a branch instruction from information stored in a relocation table, a linkage table, or both, the relocation table and the linkage table associated with a binary file and store the valid target address in a table in memory, the valid target address to validate a target address for a translated portion of a routine of the binary file.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Applicant: INTEL CORPORATION
    Inventors: KOICHI YAMADA, PALANIVELRAJAN SHANMUGAVELAYUTHAM, SRAVANI KONDA