Patents by Inventor Sreenivas Makineedi

Sreenivas Makineedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11288070
    Abstract: A method for optimization of low-level memory operations in a distributed memory storage configuration that includes receiving, at a first processor, a request to migrate data from the first processor to a second processor, where the first processor and the second processor comprise a processor and memory, and identifying a command instruction associated with the requested data. The method also includes comparing a first performance metric associated with the first processor to a second performance metric associated with the second processor, where the first performance metric and the second performance metric are associated with executing the command instruction, and where, based on the comparing, a decision to move the command instruction to the second processor is formed, and migrating, responsive to the decision, the data and the command instruction to the second processor.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: March 29, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William F. Quinn, Anil Kalavakolanu, Douglas Griffith, Sreenivas Makineedi, Mathew Accapadi
  • Patent number: 11281513
    Abstract: Embodiments are disclosed for managing heap metadata corruption. The techniques include detecting a metadata corruption error in a first heap disposed in a first region of memory. The techniques also include generating a second heap in a free memory region that is disposed beyond a break value address of a memory allocation system. The techniques further include updating a first entry for the first heap in a heap directory. Additionally, the techniques include generating a second entry for the second heap in the heap directory. The techniques also include processing a call to the memory allocation system for the first heap based on the first entry and the second entry.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sreenivas Makineedi, Srinivasa Rao Muppala, Rama Mothey Tenjarla, Vidya Makineedi, Douglas Griffith
  • Patent number: 11263114
    Abstract: Threads of a multithreaded application may be scheduled to different cores and executed in various orders and at various frequencies. Controlling how the threads are scheduled and clock rates of processor cores enables testing multiple possible execution scenarios, which may force previously unknown timing window problems to occur. These timing window problems may then be detected.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: March 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sreenivas Makineedi, Douglas Griffith, Emmanuelle Samir Hanna Matta, Evelyn Tingmay Yeung, Srinivasa Rao Muppala
  • Patent number: 11003585
    Abstract: A method for determining affinity domain information based on virtual memory address in a computing system where access to memory is non-uniform includes receiving a request to identify an affinity domain associated with a specified virtual memory address. The affinity domain includes a cluster of processors and memory local to the cluster of processors. A physical memory page corresponding to the specified virtual memory address is determined using a page table mapping a plurality of virtual memory addresses to a plurality of physical addresses. An affinity domain associated with the determined physical memory page is identified. Affinity domain information is provided for the identified affinity domain.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William F. Quinn, Anil Kalavakolanu, Douglas Griffith, Sreenivas Makineedi, Mathew Accapadi
  • Publication number: 20210132944
    Abstract: A method for optimization of low-level memory operations in a distributed memory storage configuration that includes receiving, at a first processor, a request to migrate data from the first processor to a second processor, where the first processor and the second processor comprise a processor and memory, and identifying a command instruction associated with the requested data. The method also includes comparing a first performance metric associated with the first processor to a second performance metric associated with the second processor, where the first performance metric and the second performance metric are associated with executing the command instruction, and where, based on the comparing, a decision to move the command instruction to the second processor is formed, and migrating, responsive to the decision, the data and the command instruction to the second processor.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 6, 2021
    Applicant: International Business Machines Corporation
    Inventors: William F. Quinn, Anil Kalavakolanu, DOUGLAS GRIFFITH, SREENIVAS MAKINEEDI, Mathew Accapadi
  • Patent number: 10996990
    Abstract: Embodiments include method, systems and computer program products for performing Spectre mitigation on a workload. The method includes starting, by at least one processor of a plurality of processors, a process. The at least one processor determines that the process is a kernel process. The at least one processor determines that an interrupt has occurred in response to the determination that the process is a kernel process. The at least one processor processes the interrupt in response to determining that an interrupt has occurred. The at least one processor suppresses a malware mitigation to be applied to the kernel process in response to interrupt being processed.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sreenivas Makineedi, Douglas Griffith, Srinivasa Rao Muppala, Anil Kalavakolanu, Shanna Beck
  • Publication number: 20210089428
    Abstract: Threads of a multithreaded application may be scheduled to different cores and executed in various orders and at various frequencies. Controlling how the threads are scheduled and clock rates of processor cores enables testing multiple possible execution scenarios, which may force previously unknown timing window problems to occur. These timing window problems may then be detected.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Inventors: Sreenivas Makineedi, Douglas Griffith, Emmanuelle Samir Hanna Matta, Evelyn Tingmay Yeung, Srinivasa Rao Muppala
  • Publication number: 20200387416
    Abstract: Embodiments are disclosed for managing heap metadata corruption. The techniques include detecting a metadata corruption error in a first heap disposed in a first region of memory. The techniques also include generating a second heap in a free memory region that is disposed beyond a break value address of a memory allocation system. The techniques further include updating a first entry for the first heap in a heap directory. Additionally, the techniques include generating a second entry for the second heap in the heap directory. The techniques also include processing a call to the memory allocation system for the first heap based on the first entry and the second entry.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Inventors: Sreenivas MAKINEEDI, Srinivasa Rao Muppala, Rama Mothey Tenjarla, Vidya MAKINEEDI, Douglas GRIFFITH
  • Patent number: 10838635
    Abstract: Examples of techniques for deferred disclaim of memory pages are described herein. An aspect includes, based on freeing of a last allocation on a first memory page, placing, by a processor, the first memory page on a deferred disclaim list. Another aspect includes, based on freeing of the last allocation on the first memory page, setting, by the processor, a first hidden flag in a first page table entry corresponding to the first memory page.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas Griffith, Sreenivas Makineedi, Srinivasa Rao Muppala, Evan Zoss, Mathew Accapadi, Anil Kalavakolanu
  • Publication number: 20200285405
    Abstract: Examples of techniques for deferred disclaim of memory pages are described herein. An aspect includes, based on freeing of a last allocation on a first memory page, placing, by a processor, the first memory page on a deferred disclaim list.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Inventors: DOUGLAS GRIFFITH, SREENIVAS MAKINEEDI, Srinivasa Rao Muppala, Evan Zoss, Mathew Accapadi, Anil Kalavakolanu
  • Publication number: 20200285588
    Abstract: A method for determining affinity domain information based on virtual memory address in a computing system where access to memory is non-uniform includes receiving a request to identify an affinity domain associated with a specified virtual memory address. The affinity domain includes a cluster of processors and memory local to the cluster of processors. A physical memory page corresponding to the specified virtual memory address is determined using a page table mapping a plurality of virtual memory addresses to a plurality of physical addresses. An affinity domain associated with the determined physical memory page is identified. Affinity domain information is provided for the identified affinity domain.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Inventors: William F. Quinn, Anil Kalavakolanu, Douglas Griffith, Sreenivas Makineedi, Mathew Accapadi
  • Publication number: 20200159580
    Abstract: Embodiments include method, systems and computer program products for performing Spectre mitigation on a workload. The method includes starting, by at least one processor of a plurality of processors, a process. The at least one processor determines that the process is a kernel process. The at least one processor determines that an interrupt has occurred in response to the determination that the process is a kernel process. The at least one processor processes the interrupt in response to determining that an interrupt has occurred. The at least one processor suppresses a malware mitigation to be applied to the kernel process in response to interrupt being processed.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 21, 2020
    Inventors: Sreenivas Makineedi, Douglas Griffith, Srinivasa Rao Muppala, Anil Kalavakolanu, Shanna Beck
  • Publication number: 20200065013
    Abstract: A system includes a memory system and a processing system operably coupled to the memory system. The memory system includes a kernel address space associated with a kernel of an operating system and a user address space associated with a plurality of processes configured to interface with the kernel. The processing system is configured to perform a plurality of operations including determining that one or more new memory pages are assigned to the kernel address space. A kernel submodule of the kernel associated with the one or more new memory pages is identified. Clearing of the one or more new memory pages is skipped based on a memory initialization configuration associated with the kernel submodule. Access to the one or more new memory pages is provided.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Inventors: Douglas Griffith, Reginald D. Harvey, Sreenivas Makineedi, Srinivasa Rao Muppala, Paul Vaters
  • Patent number: 10546144
    Abstract: Technical solutions are described for generating a secured system snapshot of a system. An example computer-implemented method includes receiving an instruction to generate a system snapshot. The system snapshot captures data from a computer executable object loaded in a memory. The method also includes accessing metadata that is associated with the computer executable object from a mapping list. The method also includes capturing the secured system snapshot by. Capturing the secured system snapshot includes determining sensitivity of the computer executable object by comparing the metadata with a predetermined criteria, and excluding a capture of sensitive data from the computer executable object into the system snapshot in response to the metadata of the computer executable object matching the predetermined criteria. The method also includes storing the secured system snapshot.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Douglas J. Griffith, Sreenivas Makineedi, Robert S. Manning, Srinivasa M. Raghavan
  • Patent number: 10324720
    Abstract: A system and method tests computer software using tracking bits in branch instructions to track portions of the software that have been tested. The tracking bits are bits of a branch programming instruction and may be repurposed hint bits used in the prior art to control pre-fetch of instructions. A branch tracking unit sets bits in a branch instruction of an application or program being tested. The branch tracing unit sets a first bit if a branch is taken and sets a second tracking bit if the branch is not taken. The modified program instructions can be analyzed after running the test inputs to determine if any branches in the software have not been exercised by the test inputs.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Gaurav Batra, Demetrice Browder, Douglas J. Griffith, Sreenivas Makineedi
  • Patent number: 10275248
    Abstract: A system and method tests computer software using tracking bits in branch instructions to track portions of the software that have been tested. The tracking bits are bits of a branch programming instruction and may be repurposed hint bits used in the prior art to control pre-fetch of instructions. A branch tracking unit sets bits in a branch instruction of an application or program being tested. The branch tracing unit sets a first bit if a branch is taken and sets a second tracking bit if the branch is not taken. The modified program instructions can be analyzed after running the test inputs to determine if any branches in the software have not been exercised by the test inputs.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Gaurav Batra, Demetrice Browder, Douglas J. Griffith, Sreenivas Makineedi
  • Patent number: 10001925
    Abstract: A method for setting a compression ratio for utilizing a compressed memory pool (which is backed by pinned memory) by a virtual memory manager (VMM). Compression of pages of corresponding segments can be tracked as part of a VMM paging algorithm that compresses pages to store in a compressed memory pool. A segment having pages with an average compression ratio below a threshold is identified. The identified segment pages are prevented from utilizing the compressed memory pool resulting in optimizing the use of the compressed memory pool.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: June 19, 2018
    Assignee: International Business Machines Corporation
    Inventors: Gaurav Batra, Sreenivas Makineedi
  • Patent number: 9921977
    Abstract: A method for privilege based memory pinning is provided. The method includes receiving a request to pin an amount of address space memory from a process executing on an operating system. The operating system includes a configurable mode of operation. In mandatory mode, the operating system executes the request to pin address space memory based on the role hierarchy-based privilege level of the requestor process. When the requested amount is greater than the operating system's amount of memory that can be used to pin memory, the operating system fails the request. However, when the operating can satisfy the request from processes having a lower privilege level relative to the requestor process, memory is unpinned from one or more of these processes.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sreenivas Makineedi, Srinivasa Raghavan M. Parthasarathi
  • Patent number: 9916264
    Abstract: A method for privilege based memory pinning is provided. The method includes receiving a request to pin an amount of address space memory from a process executing on an operating system. The operating system includes a configurable mode of operation. In mandatory mode, the operating system executes the request to pin address space memory based on the role hierarchy-based privilege level of the requestor process. When the requested amount is greater than the operating system's amount of memory that can be used to pin memory, the operating system fails the request. However, when the operating can satisfy the request from processes having a lower privilege level relative to the requestor process, memory is unpinned from one or more of these processes.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sreenivas Makineedi, Srinivasa Raghavan M. Parthasarathi
  • Publication number: 20170323110
    Abstract: Technical solutions are described for generating a secured system snapshot of a system. An example computer-implemented method includes receiving an instruction to generate a system snapshot. The system snapshot captures data from a computer executable object loaded in a memory. The method also includes accessing metadata that is associated with the computer executable object from a mapping list. The method also includes capturing the secured system snapshot by. Capturing the secured system snapshot includes determining sensitivity of the computer executable object by comparing the metadata with a predetermined criteria, and excluding a capture of sensitive data from the computer executable object into the system snapshot in response to the metadata of the computer executable object matching the predetermined criteria. The method also includes storing the secured system snapshot.
    Type: Application
    Filed: May 5, 2016
    Publication date: November 9, 2017
    Inventors: Douglas J. Griffith, Sreenivas Makineedi, Robert S. Manning, Srinivasa M. Raghavan