Patents by Inventor SRI CHAITRA JYOTSNA CHAVALI

SRI CHAITRA JYOTSNA CHAVALI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210193579
    Abstract: Various examples provide a semiconductor package. The semiconductor package includes a substrate having first and second opposed substantially planar major surfaces extending in an x-y direction. The package further includes a bridge die having third and fourth opposed substantially planar major surfaces extending in the x-y direction. The third substantially planar major surface of the bridge die is in direct contact with the second substantially planar major surface of the substrate. The semiconductor package further includes a through silicon via extending in a z-direction through the first substantially planar major surface of the substrate and the fourth substantially planar major surface of the bridge die. The semiconductor package further includes a power source coupled to the through silicon via, a first electronic component electronically coupled to the bridge die, and a second electronic component electronically coupled to the bridge die.
    Type: Application
    Filed: December 23, 2019
    Publication date: June 24, 2021
    Inventors: Sanka Ganesan, Robert L. Sankman, Sri Chaitra Jyotsna Chavali
  • Patent number: 11004792
    Abstract: Described are microelectronic devices including a substrate formed with multiple build-up layers, and having at least one build-up layer formed of a fiber-containing material. A substrate can include a buildup layers surrounding an embedded die, or outward of the build-up layer surrounding the embedded die that includes a fiber-containing dielectric. Multiple build-up layers located inward from a layer formed of a fiber-containing dielectric will be formed of a fiber-free dielectric.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventor: Sri Chaitra Jyotsna Chavali
  • Publication number: 20210125932
    Abstract: Embodiments include a package substrate, a semiconductor package, and a method of forming the package substrate. A package substrate includes a core substrate between a first alternate core substrate and a second alternate core substrate. The first alternate core substrate includes conductive layers and vias. The package substrate includes a dielectric layer surrounding the core and first and second alternate substrates, a first conductive layer on a top surface of the dielectric layer, and a second conductive layer on top surfaces of the core and first and second alternate substrates, where the dielectric layer is over/under the core and first and second alternate substrates. The package substrate includes a third conductive layer on bottom surfaces of the core and first and second alternate substrates. The conductive layers are coupled to the vias within the first alternate core substrate, where the conductive layers and vias couple the second and third layers.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Inventor: Sri Chaitra Jyotsna CHAVALI
  • Publication number: 20210125944
    Abstract: Embodiments include inductors and methods to form the inductors. An inductor includes a substrate layer that surrounds a magnetic layer, where the magnetic layer is embedded between the substrate layer. The inductor also includes a dielectric layer that surrounds the substrate and magnetic layers, where the dielectric layer fully embeds the substrate and magnetic layers. The inductor further includes a first conductive layer over the dielectric layer, a second conductive layer below the dielectric layer, and a plurality of plated-through-hole (PTH) vias in the dielectric and substrate layers. The PTH vias vertically extend from the first conductive layer to the second conductive layer, and the magnetic layer in between the PTH vias. The magnetic layer may have a thickness that is substantially equal to a thickness of the substrate layer, where the thickness of the magnetic layer is less than a thickness defined between the first and second conductive layers.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Inventors: William J. LAMBERT, Sri Chaitra Jyotsna CHAVALI
  • Patent number: 10980129
    Abstract: An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Sri Chaitra Jyotsna Chavali, Amruthavalli Pallavi Alur, Wei-Lun Kane Jen, Sriram Srinivasan
  • Publication number: 20210028116
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.
    Type: Application
    Filed: July 24, 2019
    Publication date: January 28, 2021
    Inventors: Sanka GANESAN, Robert L. SANKMAN, Arghya SAIN, Sri Chaitra Jyotsna CHAVALI, Lijiang WANG, Cemil GEYIK
  • Patent number: 10903137
    Abstract: According to various embodiments of the present disclosure, an electrically conductive pillar having a substrate is disclosed. The electrically conductive pillar can comprise a first portion, second portion and a third portion. The first portion and/or third portion can be formed of an electrically conductive material that can be the same or different. The second portion can be intermediate and abut both the first portion and the third portion. The second portion can comprise a solder element formed of a second electrically conductive material that differs from the electrically conductive material and has a second stiffness less than a stiffness of the electrically conductive material.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Siddharth K. Alur, Sri Chaitra Jyotsna Chavali
  • Publication number: 20210005550
    Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate having a core layer. An inductor may include a first coaxial line and a second coaxial line vertically through the core layer, and an interconnect within the package substrate coupling the first coaxial line and the second coaxial line. A first magnetic segment may surround the first coaxial line within the core layer, and a second magnetic segment may surround the second coaxial line within the core layer. In addition, a third magnetic segment may surround the interconnect and be coupled to the first magnetic segment and the second magnetic segment. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 7, 2021
    Inventors: Sri Chaitra Jyotsna CHAVALI, Tarek IBRAHIM, Wei-Lun JEN
  • Publication number: 20200312675
    Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.
    Type: Application
    Filed: June 15, 2020
    Publication date: October 1, 2020
    Inventors: Sri Chaitra Jyotsna Chavali, Siddharth K. Alur, Lilia May, Amanda E. Amanda
  • Publication number: 20200251411
    Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Applicant: Intel Corporation
    Inventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
  • Publication number: 20200221577
    Abstract: An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.
    Type: Application
    Filed: March 16, 2020
    Publication date: July 9, 2020
    Inventors: Sri Chaitra Jyotsna Chavali, Amruthavalli Palavi Alur, Wei-Lun Kane Jen, Sriram Srinivasan
  • Patent number: 10685850
    Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Sri Chaitra Jyotsna Chavali, Siddharth K. Alur, Lilia May, Amanda E. Schuckman
  • Patent number: 10672693
    Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
  • Patent number: 10658765
    Abstract: A method of forming a planar antenna on a first substrate. An antenna feedline is formed on a peelable copper film of a carrier. A dielectric with no internal conductive layer is formed on the feedline. A planar antenna is formed on one of two parallel sides of the dielectric and a feed port is formed adjacent the other parallel side. The feedline connects the antenna with the feed port. One plane of the planar antenna is configured for perpendicular attachment to a second substrate. The feedline is connected to the planar antenna by a via through the dielectric. The peelable copper is removed and the structure is etched to produce the planar antenna on the substrate. Two planar antennas on substrates can be perpendicularly attached to another substrate to form side-firing antennas.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Sri Chaitra Jyotsna Chavali, Sanka Ganesan, William J. Lambert, Debendra Mallik, Zhichao Zhang
  • Patent number: 10624213
    Abstract: An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Sri Chaitra Jyotsna Chavali, Amruthavalli Pallavi Alur, Wei-Lun Kane Jen, Sriram Srinivasan
  • Publication number: 20200105674
    Abstract: Described are microelectronic devices including a substrate formed with multiple build-up layers, and having at least one build-up layer formed of a fiber-containing material. A substrate can include a buildup layers surrounding an embedded die, or outward of the build-up layer surrounding the embedded die that includes a fiber-containing dielectric. Multiple build-up layers located inward from a layer formed of a fiber-containing dielectric will be formed of a fiber-free dielectric.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventor: Sri Chaitra Jyotsna Chavali
  • Publication number: 20200098727
    Abstract: A wire-bond memory die is coupled to a system-on-chip processor where the processor is flip-chip mounted on a semiconductor package substrate, and the wire-bond memory die is also flip-chip configured through a redistribution layer that pins out to a series of pillars that contact the semiconductor package substrate. The wire-bond memory die is stacked on the processor and the redistribution layer overhangs the processor to contact the series of pillars.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Debendra Mallik, Robert L. Sankman, Sanka Ganesan, George Vakanas, Omkar Karhade, Sri Chaitra Jyotsna Chavali, Zhaozhi George Li, Holly A. Sawyer
  • Publication number: 20200075473
    Abstract: Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.
    Type: Application
    Filed: May 23, 2017
    Publication date: March 5, 2020
    Applicant: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Rahul N. Manepalli, David Unruh, Frank Truong, Kyu Oh Lee, Junnan Zhao, Sri Chaitra Jyotsna Chavali
  • Publication number: 20200006866
    Abstract: A method of forming a planar antenna on a first substrate. An antenna feedline is formed on a peelable copper film of a carrier. A dielectric with no internal conductive layer is formed on the feedline. A planar antenna is formed on one of two parallel sides of the dielectric and a feed port is formed adjacent the other parallel side. The feedline connects the antenna with the feed port. One plane of the planar antenna is configured for perpendicular attachment to a second substrate. The feedline is connected to the planar antenna by a via through the dielectric. The peelable copper is removed and the structure is etched to produce the planar antenna on the substrate. Two planar antennas on substrates can be perpendicularly attached to another substrate to form side-firing antennas.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Sri Chaitra Jyotsna Chavali, Sanka Ganesan, William J. Lambert, Debendra Mallik, Zhichao Zhang
  • Publication number: 20200006273
    Abstract: A microelectronic device is formed including two or more structures physically and electrically engaged with one another through coupling of conductive features on the two structures. The conductive features may be configured to be tolerant of bump thickness variation in either of the structures. Such bump thickness variation tolerance can result from a contact structure on a first structure including a protrusion configured to extend in the direction of the second structure and to engage a deformable material on that second structure.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Manish Dubey, Kousik Ganesan, Suddhasattwa Nad, Thomas Heaton, Sri Chaitra Jyotsna Chavali, Amruthavalli Pallavi Alur