Patents by Inventor Sridhar Krishnamurthy

Sridhar Krishnamurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10366201
    Abstract: Closing timing for a circuit design can include displaying, using a display device, a first region having a plurality of controls corresponding to a plurality of data sets generated at different times during a phase of a design flow for a circuit design, wherein each control selects a data set associated with the control, and displaying, using the display device, a second region configured to display a list of critical paths for data sets selected from the first region using one of the plurality of controls. Closing timing further can include displaying, using the display device, a third region configured to display a representation of a target integrated circuit including layouts for the critical paths of the list for implementations of the circuit design specified by the selected data sets.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: July 30, 2019
    Assignee: XILINX, INC.
    Inventors: Aaron Ng, Sridhar Krishnamurthy, Grigor S. Gasparyan
  • Patent number: 10068048
    Abstract: The disclosure describes approaches for generating a clock tree for a circuit design. Initial clock trees are generated and elements are assigned to locations on an integrated circuit (IC). Each of the initial clock trees includes a clock root, a spine including the clock root, and branches connected to and extending from the spine. Each clock load is coupled to one of the branches. The clock tree further includes programmable delay circuits having initial delay values that are balanced. If the circuit design does not satisfy timing constraints, at least one clock root is moved from a respective first location to a respective second location.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: September 4, 2018
    Assignee: XILINX, INC.
    Inventors: Mehrdad Eslami Dehkordi, Marvin Tom, Sridhar Krishnamurthy, Frank Mueller
  • Patent number: 10042971
    Abstract: Approaches for routing clock signals of a circuit design on an IC include determining initial partitions of clock sources and clock loads. Each initial partition includes one of the clock sources and a subset of the clock loads associated with the one clock source, and initial each partition defines an area of the IC in which the one of the clock sources and the associated subset of clock loads are placed. A processor determines for each of the initial partitions, whether or not the initial partition has a congested clock region. For each initial partition determined to have a congested clock region, the processor defines a respective new partition by excluding the one of the clock sources from the new partition. The new partition includes the subset of the clock loads and does not include the one clock source. The processor then routes clock signals from the clock sources to the clock loads.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: August 7, 2018
    Assignee: XILINX, INC.
    Inventors: Mehrdad Eslami Dehkordi, Raoul Badaoui, Marvin Tom, Sridhar Krishnamurthy
  • Patent number: 9330220
    Abstract: Clock region partitioning and clock routing includes creating partitions for a plurality of clocks of a circuit design, and legalizing the partitions using a processor according to a number of clocks in each partition and assignment of clock distribution tracks. Roots for implementing clock trees of the clocks are selected within the partitions.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: May 3, 2016
    Assignee: XILINX, INC.
    Inventors: Mehrdad E. Dehkordi, Marvin Tom, Sridhar Krishnamurthy, Abhishek Joshi
  • Patent number: 9298868
    Abstract: A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: March 29, 2016
    Assignee: NVIDIA Corporation
    Inventors: Vikas Agrawal, Shrivathsa Bhargavravichandran, Binh Pham, Jay Chen, Sridhar Krishnamurthy, Umang Shah, Chi Keung Lee
  • Patent number: 9042431
    Abstract: A transceiver with non-deterministic delay characteristics is analyzed and adjusted to provide a transceiver with deterministic delay characteristics. The transceiver may be implemented with a variety of device types to support high bandwidth operation over a wide range of frequencies. Deterministic behavior allows use of the transceiver in source synchronous interfaces. The transceiver may also be dynamically analyzed and adjusted during operation as operation frequency changes.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: May 26, 2015
    Assignee: Altera Corporation
    Inventors: Venkat Yadavalli, Sridhar Krishnamurthy, Gerardo Orlando, David Richardson King, Ken Clauss, Mark Krumpoch, Peter Markou
  • Publication number: 20140380257
    Abstract: A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Inventors: Vikas AGRAWAL, Shrivathsa BHARGAVRAVICHANDRAN, Binh PHAM, Jay CHEN, Sridhar KRISHNAMURTHY, Umang SHAH, Chi Keung LEE
  • Patent number: 8448122
    Abstract: A method of implementing a circuit design within a programmable integrated circuit (IC) can include identifying an implementation directive embedded within a register transfer level (RTL) description of the circuit design and determining components of a sub-circuit of the circuit design, wherein the sub-circuit is specified by a portion of the RTL description associated with the implementation directive. The sub-circuit can be placed for the programmable IC and routed for the programmable IC according to the implementation directive. A programmatic description of the sub-circuit specifying placement and routing information can be output.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: May 21, 2013
    Assignee: Xilinx, Inc.
    Inventors: Vishal Suthar, Hasan Arslan, Sridhar Krishnamurthy, Sanjeev Kwatra, Srinivasan Dasasathyan, Rajat Aggarwal, Sudip K. Nag
  • Patent number: 8146041
    Abstract: A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made by a computer as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: March 27, 2012
    Assignee: Xilinx, Inc.
    Inventors: Sankaranarayanan Srinivasan, Sridhar Krishnamurthy, Brian D. Philofsky, Kamal Chaudhary, Anirban Rahut
  • Patent number: 8010923
    Abstract: A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: August 30, 2011
    Assignee: Xilinx, Inc.
    Inventors: Sankaranarayanan Srinivasan, Sridhar Krishnamurthy, Brian D. Philofsky, Kamal Chaudhary, Anirban Rahut
  • Patent number: 8005886
    Abstract: A networking system may include a traffic generator. The traffic generator may include a scripting module configured to create a script. The traffic generator may execute the script to send and/or receive network messages within the networking system, which may help test one or more components of the networking system. The script may include one or more entries. An entry may be configured to instruct the traffic generator to send one or more network messages.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: August 23, 2011
    Assignee: JDS Uniphase Corporation
    Inventors: Paul G. Jacobsen, Scott A. Guillaudeu, David R. Freeman, Sridhar Krishnamurthy
  • Patent number: 7926016
    Abstract: A method of configuring a logic block of a programmable logic device (PLD) during physical implementation of a circuit design, wherein ports of the logic block are selectively registered, can include identifying the logic block of the PLD, wherein the logic block is located on a critical path. For each of a plurality of selectively registerable portions of the logic block, the method can include computing input slacks and output slacks based upon potential register usage within the logic block. The method further can include determining register usage for the logic block by maximizing a function which depends upon a measure of worst case slack for pipeline stages.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: April 12, 2011
    Assignee: Xilinx, Inc.
    Inventors: Priya Sundararajan, Sridhar Krishnamurthy
  • Patent number: 7784006
    Abstract: Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, matching elements between a modified version of the circuit design and an implemented version of the circuit design are identified. Recommended placements for the matching elements are established based on placement information from the implemented version of the circuit design. An initial placement of the modified version of the circuit design is generated using the recommended placements. Timing-critical elements in the initial placement are identified. Locked placements for elements other than the timing-critical elements are established. An optimized placement of the modified version of the circuit design is generated using the locked placements.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: August 24, 2010
    Assignee: Xilinx, Inc.
    Inventors: Arnaud Duthou, Sridhar Krishnamurthy
  • Patent number: 7610573
    Abstract: A computer-implemented method of implementing a circuit design within a target integrated circuit (IC) can include, during technology mapping of the circuit design, determining a plurality of implementations of at least one sub-circuit of the circuit design and placing the circuit design on the target IC using a primary implementation of the plurality of implementations of the sub-circuit. The primary implementation of the sub-circuit can be selectively replaced with an alternate implementation of the sub-circuit selected from the plurality of implementations of the sub-circuit. The placed circuit design, including either the primary implementation or the alternate implementation of the sub-circuit, can be output.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: October 27, 2009
    Assignee: XILINX, Inc.
    Inventors: Vi Chi Chan, Tetse Jang, Sridhar Krishnamurthy, Kevin Chung
  • Patent number: 7478356
    Abstract: A method of configuring a logic block of a programmable logic device (PLD) during physical implementation of a circuit design, wherein ports of the logic block are selectively registered, can include identifying the logic block of the PLD, wherein the logic block is located on a critical path. For each of a plurality of selectively registerable portions of the logic block, the method can include computing input slacks and output slacks based upon potential register usage within the logic block. The method further can include determining register usage for the logic block by maximizing a function which depends upon a measure of worst case slack for pipeline stages.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: January 13, 2009
    Assignee: Xilinx, Inc.
    Inventors: Priya Sundararajan, Sridhar Krishnamurthy
  • Patent number: 7249335
    Abstract: Methods of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) compression technique to the resulting configuration bitstream. The methods apply placement patterns and/or routing templates to encourage the inclusion of numbers of duplicated routing paths in the routed design. The duplicated routing paths result in duplicated configuration data. Thus, a configuration bitstream implementing the routed design in the PLD includes numbers of duplicated configuration data frames, and is well-suited to benefit from MFW compression techniques.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: July 24, 2007
    Assignee: Xilinx, Inc.
    Inventors: Jay T. Young, Jeffrey V. Lindholm, Sridhar Krishnamurthy
  • Publication number: 20060267798
    Abstract: A networking system may include a traffic generator. The traffic generator may include a scripting module configured to create a script. The traffic generator may execute the script to send and/or receive network messages within the networking system, which may help test one or more components of the networking system. The script may include one or more entries. An entry may be configured to instruct the traffic generator to send one or more network messages.
    Type: Application
    Filed: May 19, 2006
    Publication date: November 30, 2006
    Applicant: FINISAR CORPORATION
    Inventors: Paul Jacobsen, Scott Guillaudeu, David Freeman, Sridhar Krishnamurthy
  • Patent number: 7143384
    Abstract: Methods of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) compression technique to the resulting configuration bitstream. The methods apply placement patterns and/or routing templates to encourage the inclusion of numbers of duplicated routing paths in the routed design. The duplicated routing paths result in duplicated configuration data. Thus, a configuration bitstream implementing the routed design in the PLD includes numbers of duplicated configuration data frames, and is well-suited to benefit from MFW compression techniques.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: November 28, 2006
    Assignee: Xilinx, Inc.
    Inventors: Jay T. Young, Jeffrey V. Lindholm, Sridhar Krishnamurthy
  • Patent number: 7111214
    Abstract: Circuit implementations and test methods enable the testing of lookup table (LUT) input paths, “stuck at” memory cell values, and carry chains. One method includes storing a first bit pattern in each LUT, configuring the carry chain to perform a wide AND function of the LUT outputs, and cycling the inputs of each LUT while comparing the carry chain output to an expected value and reporting the PLD faulty if a difference is detected. The carry chain is configured to perform a wide OR function, and the cycling step is repeated. The bit pattern within each LUT is changed to the complement of the first bit pattern by providing a series of shift commands or by otherwise storing new values in the LUT, and the configuring and cycling steps are repeated. The invention also provides PLD circuit implementations that can be used to perform the described methods.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: September 19, 2006
    Assignee: Xilinx, Inc.
    Inventors: Kamal Chaudhary, Sridhar Krishnamurthy
  • Publication number: 20060149556
    Abstract: A method and device for synchronizing data between analog and digital mediums recorded either simultaneously from a single source or recorded from different sources, which requires synchronization. User-Data recorded in analog medium is referenced with out-of-band unique digital reference-data that is generated by the interface device to mark the position of the user data. The same reference-data communicated by the device and the user-data are stored in the digital medium also and a relationship is computed and established in the form of a table between the reference-data and the positions of the recorded user-data. Whenever there is a manipulation of the User-data on either of the mediums for the purpose of viewing, listening or editing, the Reference-data in that medium is interpreted by the device and the corresponding location of the user-data in the other medium is accessed by using the table.
    Type: Application
    Filed: December 12, 2005
    Publication date: July 6, 2006
    Inventors: Sridhar Krishnamurthy, Selvaraj Murugaiyan