Patents by Inventor Sridhar Krishnamurthy

Sridhar Krishnamurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7058919
    Abstract: Methods of directly targeting specified routing resources in a PLD, e.g., routing resources that need to be tested. Test designs are produced that implement observable nets using the targeted routing resources. A PLD router is used to route from a target routing resource backwards through the routing fabric of the PLD to the source of an observable net. The net is identified based on the source, and loads of the net are identified as router load targets. The router is then used to route from the target routing resource forwards to one of the loads on the net. This process can be repeated for a list of target routing resources to provide a test design that tests as many of the targeted routing resources as possible. Additional test designs can be created to test remaining target routing resources. In other embodiments, the router routes first forwards, then backwards.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: June 6, 2006
    Assignee: Xilinx, Inc.
    Inventors: Jay T. Young, Sridhar Krishnamurthy, Jeffrey V. Lindholm, Ian L. McEwen
  • Patent number: 6975990
    Abstract: A method and device for synchronizing data between analog and digital mediums recorded either simultaneously from a single source or recorded from different sources, which requires synchronization. User-Data recorded in analog medium is referenced with out-of-band unique digital reference-data that is generated by the interface device to mark the position of the user data. The same reference-data communicated by the device and the user-data are stored in the digital medium also and a relationship is computed and established in the form of a table between the reference-data and the positions of the recorded user-data. Whenever there is a manipulation of the User-data on either of the mediums for the purpose of viewing, listening or editing, the Reference-data in that medium is interpreted by the device and the corresponding location of the user-data in the other medium is accessed by using the table.
    Type: Grant
    Filed: January 3, 2001
    Date of Patent: December 13, 2005
    Assignee: Mudakara Global Solutions
    Inventors: Sridhar Krishnamurthy, Selvaraj Murugaiyan
  • Patent number: 6944809
    Abstract: Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: September 13, 2005
    Assignee: Xilinx, Inc.
    Inventors: Andrew W. Lai, Randy J. Simmons, Teymour M. Mansour, Vincent L. Tong, Jeffrey V. Lindholm, Jay T. Young, William R. Troxel, Sridhar Krishnamurthy
  • Patent number: 6910002
    Abstract: In one embodiment, a method for specifying addressability in a memory-mapped device is disclosed. A data access primitive is used to model addressablity for the memory-mapped device. Addressability comprises an address matching function, a lane matching function and one or more bus connections. A first starting address for the memory-mapped device is specified. A first set of addressing matching function, lane matching function and one or more bus connections for the memory-mapped device is generated using the data access primitive and the first starting address.
    Type: Grant
    Filed: August 23, 2000
    Date of Patent: June 21, 2005
    Assignee: Xilinx, Inc.
    Inventors: Bart Reynolds, Cheng-I Chuang, Chukwuweta Chukwudebe, Sridhar Krishnamurthy, Damon McCormick, Tom Shui, Kai Zhu
  • Patent number: 6754760
    Abstract: Interface logic is disclosed. The interface logic comprises a first address decoder, a first set of mode logic coupled to the address decoder and a first selector coupled to the first set of mode logic. The interface logic is adaptable to connect the programmable logic to the system interconnect via one of a plurality of access modes supported by the system interconnect.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: June 22, 2004
    Assignee: Xilinx, Inc.
    Inventors: Wilson Yee, Brian Fox, Sridhar Krishnamurthy, Bart Reynolds, Steven Winegarden
  • Publication number: 20040030975
    Abstract: Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.
    Type: Application
    Filed: August 6, 2002
    Publication date: February 12, 2004
    Applicant: Xilinx, Inc.
    Inventors: Andrew W. Lai, Randy J. Simmons, Teymour M. Mansour, Vincent L. Tong, Jeffrey V. Lindholm, Jay T. Young, William R. Troxel, Sridhar Krishnamurthy
  • Patent number: 6661812
    Abstract: A bidirectional bus structure includes a first multiplexer path propagating signals in a first direction and a second multiplexer path propagating signals in a second direction. For one embodiment, the bus structure further includes a circuit for selectively combining the signals on the first and second paths and selectively propagating the signal on one of the first and second paths. For another embodiment, the bus structure further includes a logic gate for combining the signals on the first and second paths and a circuit for selectively propagating the signal on one of the first path, the second path, and an output signal of the logic gate. For both embodiments, the present invention allows multiple signals to use the bus without contention, thereby providing an extremely flexible interconnect routing resource. This bidirectional bus can selectively drive signals onto the general interconnect as well as onto a system bus in a configurable system on a chip.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: December 9, 2003
    Assignee: Triscend Corporation
    Inventors: Bart Reynolds, Sridhar Krishnamurthy
  • Patent number: 6658547
    Abstract: A method for asserting an address alignment of an address for a memory-mapped device in a logic design is disclosed. An align primitive comprising an alignment size port, an input address port and an output address port is used. The alignment size port has data indicating a desired address boundary. The input address port is used for an address to be verified against the desired address boundary. The output address port is used to provide an address that is on the desired address boundary. The address to be verified against the desired address boundary is provided at the output address port when that address meets the desired address boundary. Another method for specifying an offset address for a memory-mapped device in a logic design is disclosed. An offset primitive is used to assert an address for the memory-mapped device. The offset primitive comprises an incoming address port, an outgoing address port and an offset value port. The offset value port has a data value indicating a desired address offset.
    Type: Grant
    Filed: August 23, 2000
    Date of Patent: December 2, 2003
    Assignee: Triscend Corporation
    Inventors: Bart Reynolds, Sridhar Krishnamurthy, Damon McCormick, Kai Zhu
  • Patent number: 6574655
    Abstract: Associative management of distributed multimedia assets and associated resources using multi-domain agent-based communication between heterogeneous peers is achieved using an Asset/Resource Management (ARM) platform architecture that has an ARM Framework that is used by Asset Management Agents. The ARM Framework includes an ARM Infrastructure which is a system of protocols and libraries from which communities of agents that are grouped in logical Agent Domains are built. The agents communicate via the KQML language embedded within TCP/IP messages, advertise their capabilities and cooperate together to perform meaningful work. An XML-based language is used to embed “content” within the KQML language, providing a self-describing data representation using various character sets.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: June 3, 2003
    Assignee: Thomson Licensing SA
    Inventors: Scott A. Libert, Robert J. Woolridge, Baochun Jin, Alex C. Tran, P. Murugavel, Mark S. Hillebrandt, Suhas Joshi, Sridhar Krishnamurthy, Rajagopal Govindakrishnan
  • Patent number: 6467009
    Abstract: The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: October 15, 2002
    Assignee: Triscend Corporation
    Inventors: Steven Paul Winegarden, Bart Reynolds, Brian Fox, Jean-Didier Allegrucci, Sridhar Krishnamurthy, Danesh Tavana, Arye Ziklik, Andreas Papaliolios, Stanley S. Yang, Fung Fung Lee
  • Publication number: 20020087318
    Abstract: A method and device for synchronizing data between analog and digital mediums recorded either simultaneously from a single source or recorded from different sources, which requires synchronization. User-Data recorded in analog medium is referenced with out-of-band unique digital reference-data that is generated by the interface device to mark the position of the user data. The same reference-data communicated by the device and the user-data are stored in the digital medium also and a relationship is computed and established in the form of a table between the reference-data and the positions of the recorded user-data. Whenever there is a manipulation of the User-data on either of the mediums for the purpose of viewing, listening or editing, the Reference-data in that medium is interpreted by the device and the corresponding location of the user-data in the other medium is accessed by using the table.
    Type: Application
    Filed: January 3, 2001
    Publication date: July 4, 2002
    Inventors: Sridhar Krishnamurthy, Selvaraj Murugaiyan
  • Patent number: 6107827
    Abstract: The invention provides an FPGA comprising an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE). In one embodiment, the CLE is implemented in two similar portions called "slices". Each slice has a separate carry chain. In a CLE with four function generators, each carry chain incorporates the outputs of two function generators.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: August 22, 2000
    Assignee: Xilinx, Inc.
    Inventors: Steven P. Young, Bernard J. New, Nicolas John Camilleri, Trevor J. Bauer, Shekhar Bapat, Kamal Chaudhary, Sridhar Krishnamurthy
  • Patent number: 5963050
    Abstract: The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE) and an output multiplexer. Fast feedback paths are provided within the logic block to connect the CLE outputs to the CLE inputs, either directly or through an input multiplexer. The fast feedback paths bypass the output multiplexer and therefore provide faster feedback than can be obtained in most conventional FPGA logic blocks. In one embodiment, the fast feedback paths provide the ability for all function generators in one CLE to drive each other through fast feedback paths, regardless of how logic is mapped into the function generators of the CLE.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: October 5, 1999
    Assignee: XILINX, Inc.
    Inventors: Steven P. Young, Bernard J. New, Nicolas John Camilleri, Trevor J. Bauer, Shekhar Bapat, Kamal Chaudhary, Sridhar Krishnamurthy
  • Patent number: 5942913
    Abstract: The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. The interconnect structure includes both buffered and unbuffered interconnect lines. Some buffered interconnect lines are bidirectional, and others are unidirectional. A carefully selected mixture of unidirectional and bidirectional lines provides a balance of flexibility, silicon area, and performance.
    Type: Grant
    Filed: March 20, 1997
    Date of Patent: August 24, 1999
    Assignee: Xilinx, Inc.
    Inventors: Steven P. Young, Trevor J. Bauer, Kamal Chaudhary, Sridhar Krishnamurthy
  • Patent number: 5936424
    Abstract: According to the invention, a structure is provided for driving a bus line that is both fast and small. Instead of a plurality of tristate buffers, one for each input signal, a plurality of multiplexers or gates is connected into a tree structure. The tristate enable line of the tristate buffer becomes the control line for enabling the tree structure to place its own input signal onto the bus instead of propagating the signal already on the bus. A buffer element then allows the resulting signal to be tapped from the bus. One embodiment of the invention includes lookahead logic similar to a lookahead carry chain. This allows large numbers of input lines to be connected to a bus line while retaining high speed. The symmetrical delay of a tree structure minimizes the greatest delay and thus increases predicted speed.
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: August 10, 1999
    Assignee: Xilinx, Inc.
    Inventors: Steven P. Young, Kamal Chaudhary, Shekhar Bapat, Sridhar Krishnamurthy, Philip D. Costello
  • Patent number: 5847580
    Abstract: A multiplexer chain is coupled to two logic gates which in turn propagate their respective output signals in different directions, thereby providing bidirectional signal distribution. The output lines of multiple multiplexer chains are combined together using a logic gate chain to create a bus line with a larger number of drivers while substantially maintaining switching speed and flexibility in routability. In one embodiment, two OR chains propagate signals in opposite directions. The top OR chain combines the outputs of all the multiplexer chains to its left. Similarly, the bottom OR chain combines the outputs of all the multiplexer chains to its right. The output of the entire bus is provided at both the leftmost and the rightmost end of the OR chain. The bus output is also provided at tap points by combining the outputs of the top logic gate chain and the bottom logic gate chain using a logic gate.
    Type: Grant
    Filed: October 10, 1996
    Date of Patent: December 8, 1998
    Assignee: Xilinx, Inc.
    Inventors: Shekhar Bapat, Sridhar Krishnamurthy
  • Patent number: 5844424
    Abstract: A programmable bidirectional interconnect circuit selectively provides either a buffered connection, a non-buffered connection, or a disconnection (tristate mode). The circuit includes six transistors coupled to a buffer and two signal lines.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: December 1, 1998
    Assignee: Xilinx, Inc.
    Inventors: Sridhar Krishnamurthy, Shekhar Bapat