Abstract: A system includes multiple processors and a power controller. Each processor includes a throttling engine. The power controller is to, in response to a determination that a first power consumption level exceeds a first threshold, assert a critical signal to each throttling engine of the plurality of processors. Further, for each processor, the throttling engine of the processor is to perform a sequence of multiple throttling states while the critical signal is asserted by the power controller, where the sequence of multiple throttling states is performed according to a state machine of the throttling engine. Other embodiments are described and claimed.

Abstract: A switchable graphics management scheme, which uses performance/watt information of both the iGPU/dGPU along with system real-time resources like SoC (system-on-chip) thermal, system power budgets to decide on the right GPU for rendering tasks. The scheme uses this threshold power point information along with system resources to determine the optimized GPU for tasks rendering for all applications and use cases. As such, the scheme of adapts to each system design based on capabilities of that specific system.

Abstract: A system includes multiple processors and a power controller. Each processor includes a throttling engine. The power controller is to, in response to a determination that a first power consumption level exceeds a first threshold, assert a critical signal to each throttling engine of the plurality of processors. Further, for each processor, the throttling engine of the processor is to perform a sequence of multiple throttling states while the critical signal is asserted by the power controller, where the sequence of multiple throttling states is performed according to a state machine of the throttling engine. Other embodiments are described and claimed.

Abstract: A system includes multiple processors and a power controller. Each processor includes a throttling engine. The power controller is to, in response to a determination that a first power consumption level exceeds a first threshold, assert a critical signal to each throttling engine of the plurality of processors. Further, for each processor, the throttling engine of the processor is to perform a sequence of multiple throttling states while the critical signal is asserted by the power controller, where the sequence of multiple throttling states is performed according to a state machine of the throttling engine. Other embodiments are described and claimed.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit device. Each of the voltage regulators includes a current sensor. The frequency control block operates to provide a clock signal to each of the voltage regulators. The clock signal has a frequency based on digital information. The module operates to receive a current from the current sensor of each of the voltage regulators and provides the digital information to the frequency control block to control the frequency of the clock signal. The digital information has a value based on the current from each of the current sensors.

Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit device. Each of the voltage regulators includes a current sensor. The frequency control block operates to provide a clock signal to each of the voltage regulators. The clock signal has a frequency based on digital information. The module operates to receive a current from the current sensor of each of the voltage regulators and provides the digital information to the frequency control block to control the frequency of the clock signal. The digital information has a value based on the current from each of the current sensors.

Abstract: An apparatus system is provided which comprises: a first component to receive a first signal via a first delay circuit; a second component to receive a second signal via a second delay circuit; and one or more circuitries to tune a first delay of the first delay circuit and a second delay of the second delay circuit, based at least in part on monitoring of a voltage level.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract: A multicast path trace capability is provided for tracing a multicast path from a root node to a leaf node where the trace originates at the leaf node. The leaf node sends a multicast trace request to the root node. The root node receives the multicast trace request and initiates a path trace request for collecting path information associated with the multicast path. The root node receives at least one path trace response, in response to the path trace request, which includes path information associated with the multicast path. The root node sends a multicast trace response, including the collected path information, to the leaf node. The leaf node receives the multicast trace response including the path information. The leaf node derives end-to-end path information for the multicast path using the path information received in the multicast trace response. The multicast path trace capability may be used for tracing an MPLS multicast path (e.g.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract: A system, method and apparatus for causing network routers such as Area Border Routers (ABRs) to use a preferred tie-breaking mechanism to select one path in the event of an ERO expansion operation resulting in multiple equal cost paths.

Abstract: A system, method and apparatus for signaling path binding information between end nodes of a Generalized Label Switched Path working path to provide controlled and rapid switching by both end nodes from a failed or failing working path to a protected path.

Abstract: A method, apparatus, and machine readable storage medium is for management of an Inclusive Provider Multicast Service Interface (I-PMSI) tunnel for forwarding traffic for a given multicast flow is disclosed. Aspects of the method comprise: upon expiry of an S-PMSI_DELAY interval timer, switching the multicast flow from the I-PMSI tunnel to a Selective Provider Multicast Service Interface (S-PMSI) tunnel only if the number of active Source-to-Leaf (S2L) paths exceeds a defined first threshold of a number of S2L paths and otherwise resetting the S-PMSI_DELAY interval timer. Other aspects provide for switching the multicast flow from the I-PMSI tunnel to the S-PMSI tunnel only if the number of PE nodes associated with the S-PMSI tunnel interested in the multicast flow does not exceed a defined a second threshold.

Abstract: A system, method and apparatus for performing a constraint base shortest path computation (CSPF) in a manner excluding those nodes indicated as having failed an ERO expansion, the indication being provided via an error code within an RSVP path message associated with setup of an alternate LSP.

Abstract: A method, apparatus, and machine readable storage medium is for management of an Inclusive Provider Multicast Service Interface (I-PMSI) tunnel for forwarding traffic for a given multicast flow is disclosed. Aspects of the method comprise: upon expiry of an S-PMSI_DELAY interval timer, switching the multicast flow from the I-PMSI tunnel to a Selective Provider Multicast Service Interface (S-PMSI) tunnel only if the number of active Source-to-Leaf (S2L) paths exceeds a defined first threshold of a number of S2L paths and otherwise resetting the S-PMSI_DELAY interval timer. Other aspects provide for switching the multicast flow from the I-PMSI tunnel to the S-PMSI tunnel only if the number of PE nodes associated with the S-PMSI tunnel interested in the multicast flow does not exceed a defined a second threshold.

Abstract: A method for providing a Backup Label Switched Path for a specified Bypass Label Switch Path is disclosed. The method for providing a Backup Label Switched Path for a specified Bypass Label Switch Path includes establishing a Bypass LSP having an end-to-end path; obtaining the nodes traversed by the end-to-end path; generating a request to a path calculator which using the nodes provided on the end-to-end path calculates a path disjoint to those nodes; and signaling the calculated disjoint path as a Backup LSP for the Bypass LSP. The method for providing a Backup Label Switched Path for a specified Bypass Label Switch Path provides protection advantages over systems known in the art by providing capability for handling double failure scenarios.

Abstract: A system, method and apparatus for source redundant MVPN in which a number of Interface Indices is reduced by leaf node Incoming Label Maps (ILM) including one or more Interface Indices common to multiple tunnels.

Abstract: One example embodiment of the method includes receiving first control packets, by a first node, from a source node. The first control packets indicate the status of the source node. Whether the source node is operational and if a connection path between the first node and the source node is operational is determined based on the received first control packets. The method further includes sending a second control packet to a downstream node if the source node is non-operational, or the connection is non-operational. The second control packet includes at least one value indicating the source node is unreliable.