Patents by Inventor Srinivas Perisetty

Srinivas Perisetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7863968
    Abstract: Methods and circuits for implementing negative voltage regulators are provided. The negative voltage regulator circuit includes an operational amplifier (op-amp), a PMOS transistor, and two resistors. The op-amp is powered by positive and negative voltages, and the PMOS transistor has a gate in electrical communication with the op-amp. A first resistor is disposed between a positive reference voltage and a tap point, while the second resistor is disposed between the tap point and the output of the negative voltage regulator circuit. The use of the PMOS transistor facilitates a common drain output stage making the loop gain load independent, resulting in a stable system independent of current load.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: January 4, 2011
    Assignee: Altera Corporation
    Inventor: Srinivas Perisetty
  • Patent number: 7782581
    Abstract: An electrostatic discharge (ESD) protection circuit for protecting a component on a device includes a grounding element coupled to a protected supply voltage line of the component. A supply pass element is coupled to the protected supply voltage line of the component. The ESD protection circuit also includes a control circuit to activate the grounding component to drive the protected supply voltage line of the component to ground upon detecting an ESD event.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: August 24, 2010
    Assignee: Altera Corporation
    Inventor: Srinivas Perisetty
  • Patent number: 7675317
    Abstract: An integrated circuit is provided with adjustable transistor body bias circuitry and adjustable power supply circuitry. The adjustable circuitry may be used to selectively apply body bias voltages and power supply voltages to blocks of programmable logic, memory blocks, and other circuit blocks on the integrated circuit. The body bias voltages and power supply voltages may be identified by computer aided design tools. The body bias voltages may be used to reduce leakage currents and power consumption when high speed circuit block operation is not required. Reduced power supply voltages may also be used to reduce power consumption when high speed circuit block operation is not required. To ensure optimum switching speeds, circuit blocks for which high-speed performance is critical can be provided with minimal body bias voltage or no body bias and can be provided with maximum power supply levels.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: March 9, 2010
    Assignee: Altera Corporation
    Inventor: Srinivas Perisetty
  • Patent number: 7639041
    Abstract: An integrated circuit is provided that has circuitry containing metal-oxide-semiconductor transistors with body terminals. The body terminals may be biased with an externally supplied body bias voltage that reduces power consumption. During power-up operations, the external body bias voltage may temporarily not be available. In this situation, boost circuitry may produce an internal power supply signal that may be used in place of the unavailable external body bias voltage, thereby reducing leakage currents and power consumption during power up. A multiplexer may be used in routing an appropriate body bias signal to the transistors. The boost circuitry and multiplexer may be controlled by control signals that are generated by control logic. The control logic may produce the control signals by monitoring external and internally generated power supply voltage levels during power up operations.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: December 29, 2009
    Assignee: Altera Corporation
    Inventor: Srinivas Perisetty
  • Patent number: 7639067
    Abstract: Voltage regulator circuitry is provided that exhibits a high power supply rejection ratio and a wide output voltage range. The voltage regulator circuitry can regulate power supply voltages for circuitry on a programmable logic device such as transistor body bias circuitry and configuration random-access-memory array circuitry. The voltage regulator circuitry includes an n-channel metal-oxide-semiconductor drive transistor that is coupled between a power supply voltage terminal and an output terminal. The n-channel metal-oxide-semiconductor drive transistor has a gate that receives a control signal from an operational amplifier. A boost circuit generates an elevated power supply voltage for the operational amplifier. A programmable voltage divider is coupled to the voltage regulator's output. The operational amplifier produces the control signal by comparing a feedback signal from the voltage divider to a reference voltage.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: December 29, 2009
    Assignee: Altera Corporation
    Inventor: Srinivas Perisetty
  • Publication number: 20090303826
    Abstract: Dual port memory elements and memory array circuitry that utilizes elevated and non-elevated power supply voltages for performing reliable reading and writing operations are provided. The memory array circuitry may contain circuitry to switch a power supply line of a column of memory elements in the array to an appropriate power supply voltage during reading and writing operations. Each memory element may contain circuitry to select between power supply voltages during reading and writing operations. During reading operations, an elevated voltage may power cross-coupled inverters that store data in the memory elements while a non-elevated voltage may be used to turn on associated address transistors. During writing operations, the non-elevated voltage may power the cross-coupled inverters while the elevated voltage may be used to turn on the associated address transistors.
    Type: Application
    Filed: June 5, 2008
    Publication date: December 10, 2009
    Inventor: Srinivas Perisetty
  • Patent number: 7629831
    Abstract: Booster circuitry is provided that contains capacitor protection circuitry. The booster circuitry receives a digital input signal on an input line and provides a corresponding boosted digital output signal on an output line. The digital input signal may be received from an oscillator. The digital output signal may be a clock that is applied to a charge pump on a programmable logic device integrated circuit. The booster circuitry contains a metal-oxide-semiconductor capacitor. The capacitor protection circuitry ensures that the voltage across the capacitor in the booster circuit remains above a desired minimum voltage and below a desired maximum voltage during operation. The capacitor protection circuitry includes a control circuit that monitors the capacitor voltage when the booster circuit is operated while the oscillator is off and transistor-based circuitry that discharges one of the capacitor's terminals to a predetermined level when the booster circuit is operated while the oscillator is on.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: December 8, 2009
    Assignee: Altera Corporation
    Inventors: Srinivas Perisetty, Jeffery Chow
  • Patent number: 7592832
    Abstract: An integrated circuit is provided that contain n-channel and p-channel metal-oxide-semiconductor transistors having body terminals. Adjustable transistor body bias circuitry is provided on the integrated circuit that provides body bias voltages to the body terminals to minimize power consumption. The adjustable body bias circuitry can be controlled using programmable elements on the integrated circuit that are loaded with configuration data. The integrated circuit may be a programmable logic device integrated circuit containing programmable logic. The adjustable body bias circuitry can produce an adjustable negative body bias voltage for biasing n-channel metal-oxide-semiconductor transistors. The adjustable body bias circuitry contains a bandgap reference circuit, a charge pump circuit, and an adjustable voltage regulator.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: September 22, 2009
    Assignee: Altera Corporation
    Inventor: Srinivas Perisetty
  • Patent number: 7571413
    Abstract: A programmable integrated circuit has multiple power supply voltages. Power supply voltages are distributed using power supply distribution lines. The integrated circuit has programmable power supply voltage selection switches. Each power supply voltage selection switch has its inputs connected to the power supply distribution lines and supplies a selected power supply voltage to a circuit block at its output. Test circuits are provided for testing the power supply voltage selection switches. During testing, the power supply voltage selection switches are adjusted to produce various power supply voltages at their outputs. The test circuit associated with each switch performs voltage comparisons to determine whether the switch is functioning properly. Each test circuit produces a test result based on its voltage comparison. The test results from the test circuits are provided to a scan chain, which unloads the test results from the integrated circuit to a tester for analysis.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: August 4, 2009
    Assignee: Altera Corporation
    Inventors: Jayabrata Ghosh Dastidar, Srinivas Perisetty, Andy L. Lee
  • Patent number: 7514953
    Abstract: An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circuit that clamps the body bias path at a safe voltage when potential latch-up conditions are detected. The level of body bias signal that is generated by the body bias circuitry is adjustable. The body bias generation circuitry regulates the body bias voltage on the body bias path using a p-channel control transistor. An isolation transistor is coupled between the p-channel control transistor and the body bias path. During potential latch-up conditions, the isolation transistor is turned off to isolate the body bias path from ground. Control circuitry adjusts a body bias voltage that is applied to body terminals in the p-channel control transistor and isolation transistor.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: April 7, 2009
    Assignee: Altera Corporation
    Inventor: Srinivas Perisetty
  • Patent number: 7511932
    Abstract: The present invention is an ESD protection circuit that discharges both positive and negative electrostatic events. A preferred embodiment of the circuit comprises a first NMOS transistor having a source and drain connected between ground and an I/O pad and second and third NMOS transistors and a resistor connected in series between ground and the I/O pad. The gate and body of the first transistor and the bodies of the second and third transistors are connected to a node between the second and third transistors; the gate of the second transistor is connected to the I/O pad through a second resistor; and the gate of the third transistor is connected to ground. The second and third transistors maintain the gate and body voltage of the first transistor at the pad voltage when the pad experiences negative voltages and at ground voltage when the pad experiences positive voltages.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: March 31, 2009
    Assignee: Altera Corporation
    Inventors: Antonio Gallerano, Jeffrey T. Watt, Srinivas Perisetty, Cheng-Hsiung Huang
  • Publication number: 20090072891
    Abstract: Charge pump circuitry for an integrated circuit is provided. The integrated circuit may be a programmable integrated circuit that has programmable elements that provide static control signals. The charge pump circuitry may contain a number of stages. Each stage may include a diode and a capacitor. Oscillator and control circuitry may generate clock signals. The clock signals may be applied to the capacitors in the charge pump stages. The charge pump circuitry may provide an output voltage. A programmable voltage regulator may be used to regulate the output voltage. The static control signals may be used to adjust the oscillator and control circuitry. The static control signals may also be used to adjust the programmable voltage regulator. The capacitors in the charge pump may be based on varactors.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Inventor: Srinivas Perisetty
  • Publication number: 20090072857
    Abstract: An integrated circuit is provided with adjustable transistor body bias circuitry and adjustable power supply circuitry. The adjustable circuitry may be used to selectively apply body bias voltages and power supply voltages to blocks of programmable logic, memory blocks, and other circuit blocks on the integrated circuit. The body bias voltages and power supply voltages may be identified by computer aided design tools. The body bias voltages may be used to reduce leakage currents and power consumption when high speed circuit block operation is not required. Reduced power supply voltages may also be used to reduce power consumption when high speed circuit block operation is not required. To ensure optimum switching speeds, circuit blocks for which high-speed performance is critical can be provided with minimal body bias voltage or no body bias and can be provided with maximum power supply levels.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Inventor: Srinivas Perisetty
  • Patent number: 7501849
    Abstract: An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Body bias signals can be received from an external source or generated internally. Body bias paths are used to distribute the body bias signals to the body terminals of the metal-oxide-semiconductor transistors. The latch-up prevention circuitry may include active n-channel and p-channel metal-oxide-semiconductor transistor latch-up prevention circuitry. The latch-up prevention circuitry monitors the states of power supply signals to determine whether a potential latch-up condition is present.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: March 10, 2009
    Assignee: Altera Corporation
    Inventor: Srinivas Perisetty
  • Patent number: 7495471
    Abstract: An integrated circuit is provided that contain n-channel and p-channel metal-oxide-semiconductor transistors having body terminals. Adjustable transistor body bias circuitry is provided on the integrated circuit that provides body bias voltages to the body terminals to minimize power consumption. The adjustable body bias circuitry can be controlled using programmable elements on the integrated circuit that are loaded with configuration data. The integrated circuit may be a programmable logic device integrated circuit containing programmable logic. The adjustable body bias circuitry can produce an adjustable negative body bias voltage for biasing n-channel metal-oxide-semiconductor transistors. The adjustable body bias circuitry contains a bandgap reference circuit, a charge pump circuit, and an adjustable voltage regulator.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: February 24, 2009
    Assignee: Altera Corporation
    Inventor: Srinivas Perisetty
  • Publication number: 20080258802
    Abstract: An integrated circuit is provided that contain n-channel and p-channel metal-oxide-semiconductor transistors having body terminals. Adjustable transistor body bias circuitry is provided on the integrated circuit that provides body bias voltages to the body terminals to minimize power consumption. The adjustable body bias circuitry can be controlled using programmable elements on the integrated circuit that are loaded with configuration data. The integrated circuit may be a programmable logic device integrated circuit containing programmable logic. The adjustable body bias circuitry can produce an adjustable negative body bias voltage for biasing n-channel metal-oxide-semiconductor transistors. The adjustable body bias circuitry contains a bandgap reference circuit, a charge pump circuit, and an adjustable voltage regulator.
    Type: Application
    Filed: June 27, 2008
    Publication date: October 23, 2008
    Inventor: Srinivas Perisetty
  • Publication number: 20080263481
    Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
    Type: Application
    Filed: July 1, 2008
    Publication date: October 23, 2008
    Inventors: David Lewis, Christopher F. Lane, Sarathy Sribhashyam, Srinivas Perisetty, Tim Vanderhoek, Vaughn Betz, Thomas Yau-Tsun Wong, Andy L. Lee
  • Patent number: 7405589
    Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: July 29, 2008
    Assignee: Altera Corporation
    Inventors: David Lewis, Christopher F. Lane, Sarathy Sribhashyam, Srinivas Perisetty, Tim Vanderhoek, Vaughn Betz, Thomas Yau-Tsun Wong, Andy L. Lee
  • Publication number: 20080150575
    Abstract: An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Body bias signals can be received from an external source or generated internally. Body bias paths are used to distribute the body bias signals to the body terminals of the metal-oxide-semiconductor transistors. The latch-up prevention circuitry may include active n-channel and p-channel metal-oxide-semiconductor transistor latch-up prevention circuitry. The latch-up prevention circuitry monitors the states of power supply signals to determine whether a potential latch-up condition is present.
    Type: Application
    Filed: March 7, 2008
    Publication date: June 26, 2008
    Inventor: Srinivas Perisetty
  • Publication number: 20080094100
    Abstract: An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circuit that clamps the body bias path at a safe voltage when potential latch-up conditions are detected. The level of body bias signal that is generated by the body bias circuitry is adjustable. The body bias generation circuitry regulates the body bias voltage on the body bias path using a p-channel control transistor. An isolation transistor is coupled between the p-channel control transistor and the body bias path. During potential latch-up conditions, the isolation transistor is turned off to isolate the body bias path from ground. Control circuitry adjusts a body bias voltage that is applied to body terminals in the p-channel control transistor and isolation transistor.
    Type: Application
    Filed: December 19, 2007
    Publication date: April 24, 2008
    Applicant: ALTERA CORPORATION
    Inventor: Srinivas Perisetty