Patents by Inventor Srinivas Perisetty

Srinivas Perisetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7355437
    Abstract: An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Body bias signals can be received from an external source or generated internally. Body bias paths are used to distribute the body bias signals to the body terminals of the metal-oxide-semiconductor transistors. The latch-up prevention circuitry may include active n-channel and p-channel metal-oxide-semiconductor transistor latch-up prevention circuitry. The latch-up prevention circuitry monitors the states of power supply signals to determine whether a potential latch-up condition is present.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: April 8, 2008
    Assignee: Altera Corporation
    Inventor: Srinivas Perisetty
  • Patent number: 7330049
    Abstract: An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circuit that clamps the body bias path at a safe voltage when potential latch-up conditions are detected. The level of body bias signal that is generated by the body bias circuitry is adjustable. The body bias generation circuitry regulates the body bias voltage on the body bias path using a p-channel control transistor. An isolation transistor is coupled between the p-channel control transistor and the body bias path. During potential latch-up conditions, the isolation transistor is turned off to isolate the body bias path from ground. Control circuitry adjusts a body bias voltage that is applied to body terminals in the p-channel control transistor and isolation transistor.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: February 12, 2008
    Assignee: Altera Corporation
    Inventor: Srinivas Perisetty
  • Patent number: 7296196
    Abstract: A nonvolatile memory device requires no additional dummy bytes between receipt of a read instruction and a scanning out of data from a first target memory location requiring incorporation of redundant memory bits. A set of most significant redundant memory bits corresponding to a range of regular memory locations may be read speculatively after a particular set of the highest order address bits are received. After a complete address is received, any requirement for substitution of redundant memory bits is known. If no substitution is required, the regular memory contents are read. Any requirement for a substitution of memory bits may require replacement of the entire location. A regular read operation continues after the first location is read. In this way, complete and correct data for the memory location are available after receipt of a read instruction with no additional delay for including any required redundant memory bits.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: November 13, 2007
    Assignee: Atmel Corporation
    Inventor: Srinivas Perisetty
  • Publication number: 20070205801
    Abstract: An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Body bias signals can be received from an external source or generated internally. Body bias paths are used to distribute the body bias signals to the body terminals of the metal-oxide-semiconductor transistors. The latch-up prevention circuitry may include active n-channel and p-channel metal-oxide-semiconductor transistor latch-up prevention circuitry. The latch-up prevention circuitry monitors the states of power supply signals to determine whether a potential latch-up condition is present.
    Type: Application
    Filed: March 6, 2006
    Publication date: September 6, 2007
    Inventor: Srinivas Perisetty
  • Publication number: 20070205802
    Abstract: An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circuit that clamps the body bias path at a safe voltage when potential latch-up conditions are detected. The level of body bias signal that is generated by the body bias circuitry is adjustable. The body bias generation circuitry regulates the body bias voltage on the body bias path using a p-channel control transistor. An isolation transistor is coupled between the p-channel control transistor and the body bias path. During potential latch-up conditions, the isolation transistor is turned off to isolate the body bias path from ground. Control circuitry adjusts a body bias voltage that is applied to body terminals in the p-channel control transistor and isolation transistor.
    Type: Application
    Filed: March 6, 2006
    Publication date: September 6, 2007
    Inventor: Srinivas Perisetty
  • Publication number: 20070205824
    Abstract: An integrated circuit is provided that contain n-channel and p-channel metal-oxide-semiconductor transistors having body terminals. Adjustable transistor body bias circuitry is provided on the integrated circuit that provides body bias voltages to the body terminals to minimize power consumption. The adjustable body bias circuitry can be controlled using programmable elements on the integrated circuit that are loaded with configuration data. The integrated circuit may be a programmable logic device integrated circuit containing programmable logic. The adjustable body bias circuitry can produce an adjustable negative body bias voltage for biasing n-channel metal-oxide-semiconductor transistors. The adjustable body bias circuitry contains a bandgap reference circuit, a charge pump circuit, and an adjustable voltage regulator.
    Type: Application
    Filed: March 6, 2006
    Publication date: September 6, 2007
    Inventor: Srinivas Perisetty
  • Publication number: 20070040576
    Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
    Type: Application
    Filed: December 22, 2005
    Publication date: February 22, 2007
    Inventors: David Lewis, Christopher Lane, Sarathy Sribhashyam, Srinivas Perisetty, Tim Vanderhoek, Vaughn Betz, Thomas Wong, Andy Lee
  • Publication number: 20070022330
    Abstract: A nonvolatile memory device requires no additional dummy bytes between receipt of a read instruction and a scanning out of data from a first target memory location requiring incorporation of redundant memory bits. A set of most significant redundant memory bits corresponding to a range of regular memory locations may be read speculatively after a particular set of the highest order address bits are received. After a complete address is received, any requirement for substitution of redundant memory bits is known. If no substitution is required, the regular memory contents are read. Any requirement for a substitution of memory bits may require replacement of the entire location. A regular read operation continues after the first location is read. In this way, complete and correct data for the memory location are available after receipt of a read instruction with no additional delay for including any required redundant memory bits.
    Type: Application
    Filed: May 17, 2005
    Publication date: January 25, 2007
    Inventor: Srinivas Perisetty
  • Patent number: 6879535
    Abstract: A nonvolatile memory device, in a continuous read operation, requires no dummy bytes between receipt of a read command and commencement of a scanning out of a first target data byte. The highest order bits of a range of possible target data bytes are speculatively read while only a partial set of the highest order address bits are received. The proper set of highest order target data bits is available and scanned out at a time a complete target data address is received. During this scan out time, the remainder of the target data byte is read and prepared for scanning out starting at the next highest order bit. In this way, the data byte targeted by a read command is available immediately and continuously after receipt of the full read command and address.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: April 12, 2005
    Assignee: Atmel Corporation
    Inventor: Srinivas Perisetty