Abstract: Push-pop stack and counters added to automatic processor's program addressing and execution logic. A certain instruction, typically a load counter instruction, "pushes" the contents of the program counter (instruction address register) onto the stack (that is, loads the stack in the direction from top toward bottom). Other certain instructions, such as decrement and test counter, or special bits in all instructions decrement the last loaded counter's value by one and test for zero counter value. If the test is false, the instruction address register's contents are replaced by the top stack word and the program loop is repeated. The program loop is thus repeated until the test is true. When the test is true, the program counter addresses the next instruction in sequence and the stack is popped (its contents are shifted in the direction from the bottom toward the top of the stack), the top stack word being lost since the program loop will not be repeated.

Abstract: Two-unit architecture for a microprocessor having one unit to execute program instructions and another unit to fetch the instructions in their proper sequence, being arranged to permit the overlap of fetch and execute cycles to increase program execution speed. Each unit includes a register array for storing operands or addresses, each array having two independent read ports and two independent write ports. In the execution unit, the register array stores operands, read from a memory by the fetch unit, which are applied to an arithmetic-logic unit (ALU), and stores the result from the ALU. In the fetch unit, the array is used to store indirect addresses, which can be incremented or decremented in an adder.