Abstract: According to various aspects a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory layer disposed between the first electrode and the second electrode, wherein the memory layer includes a first memory portion having a first concentration of oxygen vacancies and a second memory portion having a second concentration of oxygen vacancies different from the first concentration of oxygen vacancies.

Abstract: A method for fabricating a ferroelectric device includes providing a lower electrode layer on a substrate, forming a retention enhancement layer by oxidizing a surface of the lower electrode layer using a gas phase oxidation process, and depositing a ferroelectric high-k metal oxide layer over the retention enhancement layer on the lower electrode layer using a vapor deposition process. The retention enhancement layer on the lower electrode layer increases the retention performance and reliability of the ferroelectric device.

Abstract: According to various aspects, a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode includes: a first electrode layer including a first material having a first microstructure; a functional layer in direct contact with the first electrode layer; and a second electrode layer in direct contact with the functional layer, the second electrode layer including a second material having a second microstructure different from the first microstructure.

Abstract: Various aspects relate to a memory cell including: a first electrode; a second electrode; and a memory element, the first electrode, the second electrode, and the memory element forming a memory capacitor; wherein the memory element includes a spontaneously polarizable layer stack which includes an alternating sequence of first sublayers and second sublayers, wherein each of the second sublayers substantially consists of a mixed material of an oxide of a first transition metal and an oxide of a second transition metal, wherein each of the first sublayers substantially consists of the oxide of the first transition metal or second transition metal; wherein a first concentration of the first transition metal and a second concentration of the second transition metal in the mixed material are substantially different from one another, and/or wherein the alternating sequence starts with one of the first sublayers and ends with another one of the first sublayers.

Abstract: Various aspects relate to a memory cell including: a first electrode; a second electrode; and a memory element disposed between the first electrode and the second electrode. The memory element includes a spontaneously polarizable material. The first electrode, the second electrode, and the memory element forming a memory capacitor. The first electrode and/or the second electrode includes: an electrically conductive electrode layer, and a functional layer comprising a semi-conductive material, wherein the functional layer is in direct physical contact with the memory element.

Abstract: Various aspects relate to a memory device including: a plurality of gate layer stacks, wherein each gate layer stack of the plurality of gate layer stacks includes a gate electrode layer and one or more electrically insulating layers; one or more channel structures extending through the plurality of gate layer stacks, wherein the plurality of gate layer stacks and the one or more channel structures correspond to a plurality of field-effect transistor based memory cells, wherein each field-effect transistor based memory cell of the plurality of field-effect transistor based memory cells includes: a gate layer portion of a gate layer stack of the plurality of gate layer stacks; a channel portion of a channel structure of the one or more channel structures; a spontaneously-polarizable portion; and a floating gate, wherein the spontaneously-polarizable portion and the floating gate are disposed between the gate layer portion and the channel portion.

Abstract: A memory cell includes a capacitive memory structure comprising a first electrode; a field-effect transistor structure comprising a gate electrode; one or more insulator layers; one or more source/drain contact structures embedded in the one or more insulator layers to electrically contact the field-effect transistor structure; and a connection structure embedded in at least one of the one or more insulator layers; and one or more electrically insulating structures in addition to the one or more insulator layers configured to prevent a leakage current-induced charging of the first electrode, the gate electrode, and the connection structure, wherein the one or more electrically insulating structures comprise: a memory charge-prevention layer disposed between the first electrode of the capacitive memory structure and at least one of the one or more insulator layers, the memory charge-prevention layer laterally surrounding the first electrode of the capacitive memory structure.

Abstract: According to various aspects a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory layer disposed between the first electrode and the second electrode, wherein the memory layer includes a first memory portion having a first concentration of oxygen vacancies and a second memory portion having a second concentration of oxygen vacancies different from the first concentration of oxygen vacancies.

Abstract: Various aspects relate to a memory cell including a field-effect transistor structure and a capacitive memory structure, wherein the capacitive memory structure includes at least one spontaneously polarizable memory element, and wherein the field-effect transistor structure includes a source region, a drain region, a channel region extending between the source region and the drain region, and a gate structure disposed at the channel region, wherein the gate structure of the field-effect transistor structure substantially overlaps the source region of the field-effect transistor structure and/or the drain region of the field-effect transistor structure.

Abstract: Various aspects relate to a memory cell, the memory cell including: a field-effect transistor structure; and a capacitive memory structure; wherein the field-effect transistor structure and the capacitive memory structure are configured to form a capacitive voltage divider; wherein the capacitive memory structure includes: a first electrode layer, a second electrode layer, and a memory element structured to have at least a first region extending from the first electrode layer to the second electrode layer and a second region extending from the first electrode layer to the second electrode layer, wherein the first region consists of a first material, wherein the second region consists of a second material, and wherein the first material is different from the second material.

Abstract: Various aspects relate to a memory cell including: a thermally insulating layer disposed over one or more metallization layers of a metallization; an embedding structure disposed over the thermally insulating layer; and a spontaneously polarizable capacitor structure disposed at least partially within the embedding structure, wherein the spontaneously polarizable capacitor structure comprises a spontaneously polarizable memory element; wherein the thermally insulating layer is configured as a heat barrier to reduce a heat transfer through the embedding structure into the one or more metallization layers.

Abstract: Various aspects relate to a memory cell including: a field-effect transistor structure, the field-effect transistor structure including a gate structure to control a current flow in a channel, the gate structure including a gate isolation and a floating gate, wherein at least a part of the gate structure extends from a surface of a semiconductor layer into the semiconductor layer; and a capacitive memory structure, the capacitive memory structure including at least two electrodes and a spontaneously polarizable layer disposed between the at least two electrodes, wherein one of the at least two electrodes is in direct physical contact with the floating gate of the field-effect transistor structure, and wherein the spontaneously polarizable layer is disposed over the surface of the semiconductor layer.

Abstract: Various aspects relate to a memory cell including: a field-effect transistor memory structure, wherein a source/drain current through the field-effect transistor memory structure is a function of a gate voltage supplied to a gate of the field-effect transistor memory structure and a memory state in which the field-effect transistor memory structure is residing in; and an access device coupled to the gate of the field-effect transistor memory structure, wherein the access device is configured to control a voltage present at the gate of the field-effect transistor memory structure.

Abstract: According to various aspects, a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode includes: a first electrode layer including a first material having a first microstructure; a functional layer in direct contact with the first electrode layer; and a second electrode layer in direct contact with the functional layer, the second electrode layer including a second material having a second microstructure different from the first microstructure.

Abstract: According to various aspects a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory layer disposed between the first electrode and the second electrode, wherein the memory layer includes a first memory portion having a first concentration of oxygen vacancies and a second memory portion having a second concentration of oxygen vacancies different from the first concentration of oxygen vacancies.

Abstract: According to various aspects, a memory cell is provided, the memory cell including: a capacitive memory structure; and a field-effect transistor structure including a gate isolation, wherein the capacitive memory structure and the field-effect transistor structure are coupled with one another to form a capacitive voltage divider, wherein the gate isolation includes at least one gate isolation layer, the at least one gate isolation layer including a material having a dielectric constant greater than 4, and wherein a thickness of the at least one gate isolation layer is in the range from 3 nm to 10 nm.

Abstract: According to various aspects, a memory cell is provided, the memory cell including: a capacitive memory structure including a first electrode; a field-effect transistor structure including a gate electrode; one or more insulator layers, one or more source/drain contact structures embedded in the one or more insulator layers to electrically contact the field-effect transistor structure, and a connection structure embedded in at least one of the one or more insulator layers, wherein the connection structure electrically conductively connects the first electrode of the capacitive memory structure and the gate electrode of the field-effect transistor structure with one another and is electrically floating, and one or more additional electrically insulating structures configured to prevent a leakage current-induced charging of the first electrode, the gate electrode, and the connection structure.

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.