Patents by Inventor Stefanie Chiras
Stefanie Chiras has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8230276Abstract: Techniques for writing to memory using adaptive write techniques. An adaptive write technique includes receiving at a computer a message including a plurality of symbols. The message is written to a memory. The writing to memory includes performing for each symbol in the message: writing a data value to a memory location in the memory and reading contents of the memory location after the data value has been written. The data value is determined at the computer in response to the symbol and to the contents of any memory locations previously read as part of writing the message to the memory. It is determined at the computer if the contents of the memory locations reflect the message. The writing is restarted at the computer in response to determining that the contents of the memory locations do not reflect the message.Type: GrantFiled: September 28, 2009Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Stefanie Chiras, Michele Franceschini, John P. Karidis, Luis A. Lastras, Mayank Sharma
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Publication number: 20110078387Abstract: Techniques for writing to memory using shared address buses. A memory device that includes a plurality of memory arrays connected to a common address bus, the common address bus used to broadcast memory addresses simultaneously to the plurality of memory arrays. Each memory array includes a plurality of memory locations and circuitry for: receiving the broadcasted memory addresses from the address bus; selecting a memory address in the memory array from a list of most recent memory addresses received from the address bus; and performing a memory access at the selected memory address, such that at a given point in time at least two of the memory arrays perform the memory access at a different broadcasted address when the memory access is a write.Type: ApplicationFiled: September 28, 2009Publication date: March 31, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stefanie Chiras, Michele Franceschini, John P. Karidis, Luis A. Lastras, Mayank Sharma
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Publication number: 20110078392Abstract: Techniques for writing to memory using adaptive write techniques. An adaptive write technique includes receiving at a computer a message including a plurality of symbols. The message is written to a memory. The writing to memory includes performing for each symbol in the message: writing a data value to a memory location in the memory and reading contents of the memory location after the data value has been written. The data value is determined at the computer in response to the symbol and to the contents of any memory locations previously read as part of writing the message to the memory. It is determined at the computer if the contents of the memory locations reflect the message. The writing is restarted at the computer in response to determining that the contents of the memory locations do not reflect the message.Type: ApplicationFiled: September 28, 2009Publication date: March 31, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stefanie Chiras, Michele Franceschini, John P. Karidis, Luis A. Lastras, Mayank Sharma
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Publication number: 20080008900Abstract: A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.Type: ApplicationFiled: September 24, 2007Publication date: January 10, 2008Inventors: Yu-Ting Cheng, Stefanie Chiras, Donald Henderson, Sung-Kwon Kang, Stephen Kilpatrick, Henry Nye, Carlos Sambucetti, Da-Yuan Shih
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Publication number: 20070148958Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: ApplicationFiled: August 4, 2006Publication date: June 28, 2007Inventors: Lawrence Clevenger, Stefanie Chiras, Timothy Dalton, James Demarest, Derren Dunn, Chester Dziobkowski, Philip Flaitz, Michael Lane, James Lloyd, Darryl Restaino, Thomas Shaw, Yun-Yu Wang, Chih-Chao Yang
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Publication number: 20060264036Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.Type: ApplicationFiled: July 24, 2006Publication date: November 23, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shyng-Tsong Chen, Stefanie Chiras, Matthew Colburn, Tomothy Dalton, Jeffrey Hedrick, Elbert Huang, Kaushik Kumar, Michael Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Nitta, Sampath Purushothaman, Robert Rosenberg, Christy Tyberg, Roy Yu
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Publication number: 20060157857Abstract: A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer.Type: ApplicationFiled: March 16, 2006Publication date: July 20, 2006Applicant: International Business Machines CorporationInventors: Michael Lane, Stefanie Chiras, Terry Spooner, Robert Rosenberg
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Publication number: 20060012014Abstract: The present invention provides a plastically and/or viscoelastically deformable layer that can be used in conjunction with a low-k dielectric (k of less than 4.0) to provide an electronic semiconductor structure having improved reliability. The deformable layer can be incorporated into various points within an electronic structure to dissipate energy within the structure that may cause the low-k dielectric material to crack or delaminate therefrom. Moreover, the presence of the deformable layer with the electronic structure improves the overall strength of the resultant structure.Type: ApplicationFiled: July 15, 2004Publication date: January 19, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shyng-Tsong Chen, Stefanie Chiras, Michael Lane, Qinghuang Lin, Robert Rosenberg, Thomas Shaw, Terry Spooner
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Publication number: 20060006070Abstract: A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer.Type: ApplicationFiled: July 9, 2004Publication date: January 12, 2006Applicant: International Business Machines CorporationInventors: Michael Lane, Stefanie Chiras, Terry Spooner, Robert Rosenberg, Daniel Edelstein
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Publication number: 20050230831Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: ApplicationFiled: April 19, 2004Publication date: October 20, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence Clevenger, Stefanie Chiras, Timothy Dalton, James Demarest, Derren Dunn, Chester Dziobkowski, Philip Flaitz, Michael Lane, James Lloyd, Darryl Restaino, Thomas Shaw, Yun-Yu Wang, Chih-Chao Yang
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Publication number: 20050127514Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.Type: ApplicationFiled: December 8, 2003Publication date: June 16, 2005Inventors: Shyng-Tsong Chen, Stefanie Chiras, Matthew Colburn, Timothy Dalton, Jeffrey Hedrick, Elbert Huang, Kaushik Kumar, Michael Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Nitta, Sampath Purushothaman, Robert Rosenberg, Christy Tyberg, Roy Yu
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Publication number: 20050127518Abstract: A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.Type: ApplicationFiled: February 2, 2005Publication date: June 16, 2005Applicant: International Business Machines CorporationInventors: Cyril Cabral, Stefanie Chiras, Emanuel Cooper, Hariklia Deligianni, Andrew Kellock, Judith Rubino, Roger Tsai
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Publication number: 20050118437Abstract: A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.Type: ApplicationFiled: December 1, 2003Publication date: June 2, 2005Inventors: Yu-Ting Cheng, Stefanie Chiras, Donald Henderson, Sung-Kwon Kang, Stephen Kilpatrick, Henry Nye, Carlos Sambucetti, Da-Yuan Shih
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Publication number: 20050118796Abstract: An electrically conductive metallic interconnect in a trench or via in a dielectric is provided by depositing a first liner layer on the walls and bottom of the trench or via; removing residual contamination from the bottom of the trench or via; depositing a second liner layer in the trench; depositing a seed layer and filling the trench with electrically conductive metallic material.Type: ApplicationFiled: November 28, 2003Publication date: June 2, 2005Inventors: Stefanie Chiras, Michael Lane, Robert Rosenberg, Terry Spooner
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Publication number: 20050104216Abstract: A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.Type: ApplicationFiled: November 18, 2003Publication date: May 19, 2005Applicant: International Business Machines CorporationInventors: Cyril Cabral, Stefanie Chiras, Emanuel Cooper, Hariklia Deligianni, Andrew Kellock, Judith Rubino, Roger Tsai