Abstract: An electronic converter has first and second input terminals, first and second output terminals, a current regulator circuit arranged between the first input terminal and an intermediate node, and input capacitor arranged between the intermediate node and the second input terminal, and an output capacitor. A control circuit block is configured to sense an input voltage, compare the regulated voltage to a reference value and generate a first signal, compare the input voltage to a lower threshold and an upper threshold and generate a second signal, switch the electronic converter between an active mode and an idle mode as a function of the first signal, and switch the electronic converter between a recharge phase and a switching phase as a function of the second signal when the electronic converter is in the active mode.

Abstract: An electronic converter has first and second input terminals, first and second output terminals, a current regulator circuit arranged between the first input terminal and an intermediate node, and input capacitor arranged between the intermediate node and the second input terminal, and an output capacitor. A control circuit block is configured to sense an input voltage, compare the regulated voltage to a reference value and generate a first signal, compare the input voltage to a lower threshold and an upper threshold and generate a second signal, switch the electronic converter between an active mode and an idle mode as a function of the first signal, and switch the electronic converter between a recharge phase and a switching phase as a function of the second signal when the electronic converter is in the active mode.

Abstract: An embodiment of a method for detecting permanent faults of an address decoder of an electronic memory device including a memory block formed by a plurality of memory cells, including the steps of: selecting an address, which identifies a selected set of memory cells; writing at the selected address a code word generated on the basis of an information word, of the selected address, and of an error-correction code; and then detecting an error within a word stored at the selected address. The method moreover includes the steps of: selecting a set of excitation addresses; writing a test word at the selected address, and then writing an excitation word at each excitation address; and next comparing the test word with a new word stored at the selected address.

Abstract: A circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal, and an output for providing a flag output signal, the latch circuit being clocked by a first clock signal, a first transistor having a drain coupled to the output of the latch circuit, a gate for receiving a second clock signal, and a source, and a second transistor having a drain coupled to the source of the first transistor, a gate for receiving a third clock signal, and a source coupled to ground.

Abstract: A circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal, and an output for providing a flag output signal, the latch circuit being clocked by a first clock signal, a first transistor having a drain coupled to the output of the latch circuit, a gate for receiving a second clock signal, and a source, and a second transistor having a drain coupled to the source of the first transistor, a gate for receiving a third clock signal, and a source coupled to ground.