Patents by Inventor Stephan A. Cohen
Stephan A. Cohen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10224242Abstract: Semiconductor devices with low-resistivity metallic interconnect structures are provided. For example, a sacrificial dielectric layer is formed on a substrate, and patterned to form an opening in the sacrificial dielectric layer. The opening is filled with a metallic material to form a metallic interconnect structure, and the sacrificial dielectric layer is removed to expose the metallic interconnect structure. A heat treatment process is applied to the exposed metallic interconnect structure to modulate a microstructure of the metallic material of the metallic interconnect structure from a first microstructure to a second microstructure. A conformal liner layer is selectively deposited on exposed surfaces of the metallic interconnect structure, subsequent to the heat treatment process.Type: GrantFiled: November 14, 2017Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Stephan A. Cohen
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Patent number: 10204823Abstract: A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.Type: GrantFiled: December 28, 2017Date of Patent: February 12, 2019Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Stephan A. Cohen, Joel P. de Souza, Karen A. Nummy, Daniel J. Poindexter, Devendra K. Sadana
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Publication number: 20180122688Abstract: A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.Type: ApplicationFiled: December 28, 2017Publication date: May 3, 2018Inventors: Stephen W. Bedell, Stephan A. Cohen, Joel P. de Souza, Karen A. Nummy, Daniel J. Poindexter, Devendra K. Sadana
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Patent number: 9922866Abstract: A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.Type: GrantFiled: July 31, 2015Date of Patent: March 20, 2018Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Stephan A. Cohen, Joel P. de Souza, Karen A. Nummy, Daniel J. Poindexter, Devendra K. Sadana
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Patent number: 9698043Abstract: A substrate incorporating semiconductor regions electrically isolated by shallow trenches filled with hexagonal, textured or columnar boron nitride. A process for filling shallow trenches in a semiconductor substrate with columnar textured boron nitride using pulsed plasma enhanced chemical vapor deposition (Pulsed PECVD) and plasma assisted atomic layer deposition (PAALD).Type: GrantFiled: May 20, 2016Date of Patent: July 4, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Stephan A. Cohen, Alfred Grill, Deborah A. Neumayer
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Patent number: 9613900Abstract: An interconnect structure includes a first dielectric material having an undercut region located at an upper surface thereof. A first conductive structure is located above a first area of the undercut region. The first conductive structure comprises a first conductive metal portion having a diffusion barrier portion located on one sidewall surface of the first conductive metal portion and having a metal liner located on another sidewall surface and a bottom surface of the first conductive metal portion. A second conductive structure is located above a second area of the undercut region. The second conductive structure comprises a second conductive material portion having a diffusion barrier portion located on one sidewall surface of the second conductive material portion and having a metal liner located on another sidewall surface and a bottom surface of the second conductive metal portion. A gap is located between the first and second conductive structures.Type: GrantFiled: February 1, 2016Date of Patent: April 4, 2017Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Stephan A. Cohen, Eric G. Liniger
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Publication number: 20170033001Abstract: A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.Type: ApplicationFiled: July 31, 2015Publication date: February 2, 2017Inventors: Stephen W. Bedell, Stephan A. Cohen, Joel P. de Souza, Karen A. Nummy, Daniel J. Poindexter, Devendra K. Sadana
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Publication number: 20160148867Abstract: An interconnect structure includes a first dielectric material having an undercut region located at an upper surface thereof. A first conductive structure is located above a first area of the undercut region. The first conductive structure comprises a first conductive metal portion having a diffusion barrier portion located on one sidewall surface of the first conductive metal portion and having a metal liner located on another sidewall surface and a bottom surface of the first conductive metal portion. A second conductive structure is located above a second area of the undercut region. The second conductive structure comprises a second conductive material portion having a diffusion barrier portion located on one sidewall surface of the second conductive material portion and having a metal liner located on another sidewall surface and a bottom surface of the second conductive metal portion. A gap is located between the first and second conductive structures.Type: ApplicationFiled: February 1, 2016Publication date: May 26, 2016Inventors: Chih-Chao Yang, Stephan A. Cohen, Eric G. Liniger
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Patent number: 9281211Abstract: An interconnect structure includes a first dielectric material having an undercut region located at an upper surface thereof. A first conductive structure is located above a first area of the undercut region. The first conductive structure comprises a first conductive metal portion having a diffusion barrier portion located on one sidewall surface of the first conductive metal portion and having a metal liner located on another sidewall surface and a bottom surface of the first conductive metal portion. A second conductive structure is located above a second area of the undercut region. The second conductive structure comprises a second conductive material portion having a diffusion barrier portion located on one sidewall surface of the second conductive material portion and having a metal liner located on another sidewall surface and a bottom surface of the second conductive metal portion. A gap is located between the first and second conductive structures.Type: GrantFiled: February 10, 2014Date of Patent: March 8, 2016Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Stephan A. Cohen, Eric G. Liniger
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Publication number: 20150228572Abstract: An interconnect structure includes a first dielectric material having an undercut region located at an upper surface thereof. A first conductive structure is located above a first area of the undercut region. The first conductive structure comprises a first conductive metal portion having a diffusion barrier portion located on one sidewall surface of the first conductive metal portion and having a metal liner located on another sidewall surface and a bottom surface of the first conductive metal portion. A second conductive structure is located above a second area of the undercut region. The second conductive structure comprises a second conductive material portion having a diffusion barrier portion located on one sidewall surface of the second conductive material portion and having a metal liner located on another sidewall surface and a bottom surface of the second conductive metal portion. A gap is located between the first and second conductive structures.Type: ApplicationFiled: February 10, 2014Publication date: August 13, 2015Applicant: International Business Machines CorporationInventors: Chih-Chao Yang, Stephan A. Cohen, Eric G. Liniger
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Patent number: 9006895Abstract: A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation process is then performed which partially or completely converts the metallic residues into nitrided metallic residues. During the nitridization process, a surface region of the interconnect dielectric material and a surface region of the metal cap also become nitrided.Type: GrantFiled: September 16, 2013Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Stephan A. Cohen
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Patent number: 8962479Abstract: A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation process is then performed which partially or completely converts the metallic residues into nitrided metallic residues. During the nitridization process, a surface region of the interconnect dielectric material and a surface region of the metal cap also become nitrided.Type: GrantFiled: May 10, 2013Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Stephan A. Cohen
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Publication number: 20140332960Abstract: A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation process is then performed which partially or completely converts the metallic residues into nitrided metallic residues. During the nitridization process, a surface region of the interconnect dielectric material and a surface region of the metal cap also become nitrided.Type: ApplicationFiled: September 16, 2013Publication date: November 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Stephan A. Cohen
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Publication number: 20140332964Abstract: A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation process is then performed which partially or completely converts the metallic residues into nitrided metallic residues. During the nitridization process, a surface region of the interconnect dielectric material and a surface region of the metal cap also become nitrided.Type: ApplicationFiled: May 10, 2013Publication date: November 13, 2014Applicant: International Business Machines CorporationInventors: Chih-Chao Yang, Stephan A. Cohen
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Publication number: 20140216342Abstract: An interconnect conductive metal used in forming an interconnect structure can be formed using a method in which deposition of a metal liner and a reflow anneal are performed in a same multi-chambered processing system without exposing the structure to air between the steps of deposition and reflow annealing. In the disclosure, an interconnect dielectric material including an opening is placed within the multi-chambered processing system and then the interconnect dielectric material is transferred, under vacuum, to a deposition chamber in which the metal liner is deposited. The interconnect dielectric material including the metal liner is then transferred, under the same vacuum, to an annealing chamber in which a reflow anneal is performed.Type: ApplicationFiled: September 10, 2013Publication date: August 7, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Stephan A. Cohen, Joseph F. Maniscalco
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Publication number: 20130333923Abstract: A layer of silicon nitride having a thickness from 0.5 nanometers to 2.4 nanometers is deposited on a substrate. A plasma nitridation process is carried out on the layer. These steps are repeated for a plurality of additional layers of silicon nitride, until a predetermined thickness is attained. Such steps can be used to provide a multilayer silicon nitride dielectric formed on a substrate having an upper surface of dielectric material with Cu and other conductors embedded within, and a plurality of steps. The multilayer silicon nitride dielectric has a plurality of individual layers each having a thickness from 0.5 nanometers to 2.4 nanometers, and the multilayer silicon nitride dielectric conformally covers the steps of the substrate with a conformality of at least seventy percent. A multilayer silicon nitride dielectric, and a multilevel back end of line interconnect wiring structure using same, are also provided.Type: ApplicationFiled: June 13, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mihaela Balseanu, Stephan A. Cohen, Alfred Grill, Thomas J. Haigh, JR., Son V. Nguyen, Mei-Yee Shek, Hosadurga Shobha, Li-Qun Xia
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Patent number: 8536069Abstract: The present disclosure provides a multilayered cap (i.e., migration barrier) that conforms to the substrate (i.e., interconnect structure) below. The multilayered cap, which can be located atop at least one interconnect level of an interconnect structure, includes, from bottom to top, a first layer comprising silicon nitride and a second layer comprising at least one of boron nitride and carbon boron nitride.Type: GrantFiled: September 12, 2012Date of Patent: September 17, 2013Assignees: International Business Machines Corporation, Applied Materials, Inc.Inventors: Mihaela Balseanu, Stephan A. Cohen, Alfred Grill, Thomas J. Haigh, Jr., Son V. Nguyen, Li-Qun Xia
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Patent number: D779812Type: GrantFiled: November 30, 2015Date of Patent: February 28, 2017Inventor: Stephan Cohen
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Patent number: D781371Type: GrantFiled: November 6, 2015Date of Patent: March 14, 2017Inventor: Stephan Cohen
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Patent number: D1009983Type: GrantFiled: July 30, 2021Date of Patent: January 2, 2024Inventor: Stephan Cohen