Patents by Inventor Stephan J. Jourdan

Stephan J. Jourdan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10241952
    Abstract: Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Ravi Rajwar, Robert A. Mayer, Stephan J. Jourdan, Lily Pao Looi
  • Publication number: 20160085711
    Abstract: Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 24, 2016
    Applicant: Intel Corporation
    Inventors: Ravi Rajwar, Robert A. Mayer, Stephan J. Jourdan, Lily Pao Looi
  • Patent number: 9146610
    Abstract: Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: September 29, 2015
    Assignee: Intel Corporation
    Inventors: Ravi Rajwar, Robert A. Mayer, Stephan J. Jourdan, Lily Pao Looi
  • Patent number: 9110666
    Abstract: Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: August 18, 2015
    Assignee: Intel Corporation
    Inventors: Ravi Rajwar, Robert A. Mayer, Stephan J. Jourdan, Lily Pao Looi
  • Patent number: 8850250
    Abstract: Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Lily Pao Looi, Stephan J. Jourdan, Selim Bilgin, Sin S. Tan, Anant S. Deval, Srikanth T. Srinivasan
  • Patent number: 8782456
    Abstract: Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Sin S. Tan, Srikanth T. Srinivasan, Sivakumar Radhakrishnan, Stephan J. Jourdan, Lily Pao Looi
  • Patent number: 8291196
    Abstract: Apparatuses and methods for dead instruction identification are disclosed. In one embodiment, an apparatus includes an instruction buffer and a dead instruction identifier. The instruction buffer is to store an instruction stream having a single entry point and a single exit point. The dead instruction identifier is to identify dead instructions based on a forward pass through the instruction stream.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: October 16, 2012
    Assignee: Intel Corporation
    Inventors: Stephan J. Jourdan, Matthew C. Merten, Alexandre J. Farcy
  • Patent number: 8285976
    Abstract: A branch predicting apparatus is disclosed that reduces branch mispredictions in a processor. The branch prediction apparatus includes a base misprediction history register. The branch prediction apparatus includes a meta predictor that receives an index value and a branch prediction to generate a misprediction value in accordance with the base misprediction history register. The branch prediction apparatus also includes a logic gate that receives the branch prediction and the misprediction value to generate a final prediction. The final prediction may be used to predict whether a branch is taken or not taken.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: October 9, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Stephan J. Jourdan, Adi Yoaz, Mattan Erez, Ronny Ronen
  • Patent number: 8275560
    Abstract: A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: September 25, 2012
    Assignee: Intel Corporation
    Inventors: Sivakumar Radhakrishnan, Sin S. Tan, Stephan J. Jourdan, Lily P. Looi, Yi-Feng Liu
  • Publication number: 20120079159
    Abstract: Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
    Type: Application
    Filed: March 4, 2011
    Publication date: March 29, 2012
    Inventors: Ravi Rajwar, Robert A. Mayer, Stephan J. Jourdan, Lily Pao Looi
  • Publication number: 20110296216
    Abstract: Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.
    Type: Application
    Filed: June 1, 2010
    Publication date: December 1, 2011
    Inventors: Lily Pao Looi, Stephan J. Jourdan, Selim Bilgin, Sin S. Tan, Anant S. Deval, Srikanth T. Srinivasan
  • Publication number: 20110296222
    Abstract: Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.
    Type: Application
    Filed: December 24, 2010
    Publication date: December 1, 2011
    Inventors: Sin S. Tan, Srikanth T. Srinivasan, Sivakumar Radhakrishnan, Stephan J. Jourdan, Lily Pao Looi
  • Publication number: 20110060931
    Abstract: A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts.
    Type: Application
    Filed: September 10, 2009
    Publication date: March 10, 2011
    Inventors: SIVAKUMAR RADHAKRISHNAN, Sin S. Tan, Stephan J. Jourdan, Lily P. Lool, Yi-Feng Liu
  • Patent number: 7797683
    Abstract: Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: September 14, 2010
    Assignee: Intel Corporation
    Inventors: Per H. Hammarlund, Stephan J. Jourdan, Pierre Michaud, Alexandre J. Farcy, Morris Marden, Robert L. Hinton, Douglas M. Carmean
  • Patent number: 7757065
    Abstract: In a front-end system for a processor, a recording scheme for instruction segments stores the instructions in reverse program order. Instruction segments may be traces, extended blocks or basic blocks. By storing the instructions in reverse program order, the instruction segment is easily extended to include additional instructions. The instruction segments may be extended without having to re-index tag arrays, pointers that associate instruction segments with other instruction segments.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: July 13, 2010
    Assignee: Intel Corporation
    Inventors: Stephan J. Jourdan, Ronny Ronen, Lihu Rappoport
  • Patent number: 7711898
    Abstract: Embodiments of the present invention relate to a system and method for implementing functions of a register translation table of a computer processor, with reduced area requirements as compared to known arrangements. In one embodiment, an apparatus may comprise a register alias table cache to map a logical register to a physical register. The register alias table cache may have a capacity corresponding to a subset of architectural logical registers. The apparatus may further comprise store logic coupled to the cache to perform operations to save an existing content of the physical register if a cache entry corresponding to the logical register is evicted from the cache. The apparatus may also comprise load logic coupled to the cache to perform operations to load a content to the physical register and to form a new entry in the cache if a needed mapping is not present in the cache.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Avinash Sodani, Stephan J. Jourdan, Samie B. Samaan
  • Patent number: 7644236
    Abstract: A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: January 5, 2010
    Assignee: Intel Corporation
    Inventors: Adi Yoaz, Ronny Ronen, Lihu Rappoport, Mattan Erez, Stephan J. Jourdan, Bob Valentine
  • Patent number: 7562206
    Abstract: Microarchitecture policies and structures to predict execution clusters and facilitate inter-cluster communication are disclosed. In disclosed embodiments, sequentially ordered instructions are decoded into micro-operations. Execution of one set of micro-operations is predicted to involve execution resources to perform memory access operations and inter-cluster communication, but not to perform branching operations. Execution of a second set of micro-operations is predicted to involve execution resources to perform branching operations but not to perform memory access operations. The micro-operations are partitioned for execution in accordance with these predictions, the first set of micro-operations to a first cluster of execution resources and the second set of micro-operations to a second cluster of execution resources. The first and second sets of micro-operations are executed out of sequential order and are retired to represent their sequential instruction ordering.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: July 14, 2009
    Assignee: Intel Corporation
    Inventors: Avinash Sodani, Alexandre J. Farcy, Stephan J. Jourdan, Per Hammarlund, Mark C. Davis
  • Patent number: 7539850
    Abstract: In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to program instructions matches values associated with previously executed instructions. If so, the logical register associated with the newly executed instruction shares the physical register. Also, deadlock preventatives measures may be integrated into a register allocation unit in a manner that “steals” a physical register from a younger executed instruction when a value from an older instruction is generated-in a processor core.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Stephan J. Jourdan, Ronny Ronen, Michael Bekerman
  • Patent number: 7529913
    Abstract: Embodiments of the present invention relate to a method and system for providing virtual identifiers corresponding to physical registers in a computer processor. According to the embodiments, the virtual identifiers may be used to represent the physical registers during operations in a pipeline of the processor.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: May 5, 2009
    Assignee: Intel Corporation
    Inventors: Avinash Sodani, Per H. Hammarlund, Stephan J. Jourdan