Abstract: A fastening screw (2) comprising a threaded shank (21) having an external thread, a screw head (23), characterized in that a truncated circular cone section (22) is provided axially between the screw head (23) and the threaded shank (21).

Abstract: The invention relates to a conveyor device (1), designed: to receive an item to be conveyed (F2), more particularly a meat item, at a receiving region (A1) from an upstream feed device (110); to transfer the item to be conveyed (F2) at a transfer region (A3); to hand over the item to be conveyed (F2) in a handover region (A2) from the receiving region (A1) to the transfer region (A3), wherein the conveyor device (1) comprises a plurality of discrete transport units (21), wherein the transport units (21) are more particularly arranged in circulation, characterized in that the transport units (21) are designed: to receive the item to be conveyed (F2) at the receiving region (A1), to be handed over between the receiving region (A1) and the transfer region (A3), and to hand over the item to be conveyed (F2) at the transfer region (A3).

Abstract: A pressure vessel with a flushing lance, a transport container with pressure vessels and methods of filling and producing this pressure vessel are disclosed which comprises an inner vessel, an outer layer applied on the inner vessel, a valve connection piece arranged on one of the terminal caps of the inner vessel and a hollow flushing lance that is open to the outside and is guided through the valve connection piece and held therein in a sealing manner, wherein the flushing lance protrudes into the storage volume and is provided with a perforation along its entire length up to a first end of the flushing lance facing the terminal cap that lies opposite the valve connection piece in the storage volume for a gas exchange with the storage volume, wherein the flushing lance extends to the terminal cap which lies opposite the valve connection piece.

Abstract: The invention relates to a method for the disposal of a composite material, in particular a composite material contaminated, for example, by radioactivity and containing fluorine impurities. The inventive method for the disposal of a component containing a composite material with a composite matrix and a technical fiber, is characterized in that the component is chemically gasified, wherein the composite material is technically completely decomposed into its basic components, wherein in a first step the composite matrix is dissolved and in a subsequent step the remaining starting materials and intermediate products are thermally decomposed and reacted with added process gases, wherein at least in the subsequent step a reactive gas is supplied and the subsequent step is conducted endothermically.

Abstract: A pressure vessel is disclosed having an inner vessel made of an inner-vessel material and an outer layer applied thereon as well as a valve-connection piece with a two-part sealing cone and outer piece, the sealing cone being positioned on an inner face of a protrusion of the inner vessel and the outer piece for generating a sealing pressure being positioned between the two-part sealing cone, the protrusion and the outer piece on an outer face of the protrusion. The outer piece includes a suitably shaped groove having a first and a second edge for receiving a sealing ring that seals under the sealing pressure, wherein the groove and the sealing ring are dimensioned such that, under the sealing pressure and due to the plastic deformability, first and second sealing beads project at least into two gaps between the sealing ring and form the first and second edge.

Abstract: A pressure vessel with a flushing lance, a transport container with pressure vessels and methods of filling and producing this pressure vessel are disclosed which comprises an inner vessel, an outer layer applied on the inner vessel, a valve connection piece arranged on one of the terminal caps of the inner vessel and a hollow flushing lance that is open to the outside and is guided through the valve connection piece and held therein in a sealing manner, wherein the flushing lance protrudes into the storage volume and is provided with a perforation along its entire length up to a first end of the flushing lance facing the terminal cap that lies opposite the valve connection piece in the storage volume for a gas exchange with the storage volume, wherein the flushing lance extends to the terminal cap which lies opposite the valve connection piece.

Abstract: A pressure vessel is disclosed having an inner vessel made of an inner-vessel material and an outer layer applied thereon as well as a valve-connection piece with a two-part sealing cone and outer piece, the sealing cone being positioned on an inner face of a protrusion of the inner vessel and the outer piece for generating a sealing pressure being positioned between the two-part sealing cone, the protrusion and the outer piece on an outer face of the protrusion. The outer piece includes a suitably shaped groove having a first and a second edge for receiving a sealing ring that seals under the sealing pressure, wherein the groove and the sealing ring are dimensioned such that, under the sealing pressure and due to the plastic deformability, first and second sealing beads project at least into two gaps between the sealing ring and form the first and second edge.

Abstract: A method for forming field effect transistors (FETs) in a multiple wafers per batch epi-reactor includes, providing substrates having therein at least one semiconductor (SC) region with a substantially flat outer surface, modifying such substantially flat outer surface to form a convex-outward curved surface, forming an epitaxial semiconductor layer on the curved surface, and incorporating the epitaxial layer in a field effect transistor formed on the substrate. Where the SC region is of silicon, the epitaxial layer can include silicon-germanium. In a preferred embodiment, the epi-layer forms part of the FET channel. Because of the convex-outward curved surface, the epi-layer grown thereon has much more uniform thickness even when formed in a high volume reactor holding as many as 100 or more substrates per batch. FETs with much more uniform properties are obtained, thereby greatly increasing the manufacturing yield and reducing the cost.

Abstract: A semiconductor device includes drain and source regions positioned in an active region of a transistor and a channel region positioned laterally between the drain and source regions that includes a semiconductor base material and a threshold voltage adjusting semiconductor material positioned on the semiconductor base material. A gate electrode structure is positioned on the threshold voltage adjusting semiconductor material, and a strain-inducing semiconductor alloy including a first semiconductor material and a second semiconductor material positioned above the first semiconductor material is embedded in the semiconductor base material of the active region.

Abstract: A semiconductor device includes drain and source regions positioned in an active region of a transistor and a channel region positioned laterally between the drain and source regions that includes a semiconductor base material and a threshold voltage adjusting semiconductor material positioned on the semiconductor base material. A gate electrode structure is positioned on the threshold voltage adjusting semiconductor material, and a strain-inducing semiconductor alloy including a first semiconductor material and a second semiconductor material positioned above the first semiconductor material is embedded in the semiconductor base material of the active region.

Abstract: Different strain-inducing semiconductor alloys may be incorporated into the drain and source areas of different transistors in sophisticated semiconductor devices by at least patterning the corresponding cavities in a common manufacturing sequence. Thus, the etch process may be performed on the basis of a high degree of uniformity and the subsequent epitaxial growth processes may, in some illustrative embodiments, be accomplished on the basis of only one additional lithography step.

Abstract: An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.

Abstract: In sophisticated semiconductor devices, transistors may be formed on the basis of a high-k metal gate electrode structure provided in an early manufacturing phase, wherein an efficient strain-inducing mechanism may be implemented by using an embedded strain-inducing semiconductor alloy. In order to reduce the number of lattice defects and provide enhanced etch resistivity in a critical zone, i.e., in a zone in which a threshold voltage adjusting semiconductor alloy and the strain-inducing semiconductor material are positioned in close proximity, an efficient buffer material or seed material, such as a silicon material, is incorporated, which may be accomplished during the selective epitaxial growth process.

Abstract: Disclosed herein are various methods of forming a silicon/germanium protection layer above source/drain regions of a transistor. One method disclosed herein includes forming a plurality of recesses in a substrate proximate the gate structure, forming a semiconductor material in the recesses, forming at least one layer of silicon above the semiconductor material, and forming a cap layer comprised of silicon germanium on the layer of silicon. One device disclosed herein includes a gate structure positioned above a substrate, a plurality of recesses formed in the substrate proximate the gate structure, at least one layer of semiconductor material positioned at least partially in the recesses, a layer of silicon positioned above the at least one layer of semiconductor material, and a cap layer comprised of silicon/germanium positioned on the layer of silicon.

Abstract: A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.

Abstract: A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material.

Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers.

Abstract: A semiconductor device includes a gate electrode structure of a transistor, the gate electrode structure being positioned above a semiconductor region and having a gate insulation layer that includes a high-k dielectric material, a metal-containing cap material positioned above the gate insulation layer, and a gate electrode material positioned above the metal-containing cap material. A bottom portion of the gate electrode structure has a first length and an upper portion of the gate electrode structure has a second length that is different than the first length, wherein the first length is approximately 50 nm or less. A strain-inducing semiconductor alloy is embedded in the semiconductor region laterally adjacent to the bottom portion of the gate electrode structure, and drain and source regions are at least partially positioned in the strain-inducing semiconductor alloy.

Abstract: Disclosed herein are various methods of forming a layer of silicon on a layer of silicon/germanium. In one example, a method disclosed herein includes forming a silicon/germanium material on a semiconducting substrate, after forming the silicon/germanium material, performing a heating process to raise a temperature of the substrate to a desired silicon formation temperature while flowing a silicon-containing precursor and a chlorine-containing precursor into the deposition chamber during the heating process, and, after the temperature of the substrate reaches the desired silicon formation temperature, forming a layer of silicon on the silicon/germanium material.

Abstract: An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.