Patents by Inventor Stephen Arion Meisner

Stephen Arion Meisner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuits having dielectric layers including an anti-reflective coating
    Patent number: 11171200
    Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: November 9, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Poornika Fernandes, David Matthew Curran, Stephen Arion Meisner, Bhaskar Srinivasan, Guruvayurappan S. Mathur, Scott William Jessen, Shih Chang Chang, Russell Duane Fields, Thomas Terrance Lynch
  • Increasing exposure tool alignment signal strength for a ferroelectric capacitor layer
    Patent number: 8586130
    Abstract: An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: November 19, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Stephen Arion Meisner, Scott R. Summerfelt
  • Increasing Exposure Tool Alignment Signal Strength for a Ferroelectric Capacitor Layer
    Publication number: 20110014360
    Abstract: An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.
    Type: Application
    Filed: September 24, 2010
    Publication date: January 20, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Stephen Arion Meisner, Scott R. Summerfelt