Abstract: Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system identifies, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system generates one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system then corrects the set of bits based on the candidate set of bits identified as error-free.

Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.

Abstract: Methods, systems, and devices for inserting temperature information into a codeword are described. A memory system may determine that a predetermined set of bits of a codeword has been received. Based on determining that the predetermine set of bits has been received, the memory system may replace bits of the codeword with temperature information that indicates a temperature of the memory system. The memory system may then store the codeword comprising the temperature information in a memory array.

Abstract: Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system may identify, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system may generate one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system may then correct the set of bits based on the candidate set of bits identified as error-free.

Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.

Abstract: Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system identifies, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system generates one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system then corrects the set of bits based on the candidate set of bits identified as error-free.

Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.

Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller generally includes a processor, a cache and a hardware assist circuit. The processor may be configured to initiate a recycle operation by generation of a start index. The cache may be configured to buffer a first level of a map and less than all of a second level of the map. The hardware assist circuit may be configured to search through the first level or any portions of the second level of the map in the cache in response to the start index, and notify the processor in response to the search detecting one or more blocks in the memory that contain valid data to be recycled.

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller generally includes a processor, a cache and a hardware assist circuit. The processor may be configured to initiate a recycle operation by generation of a start index. The cache may be configured to buffer a first level of a map and less than all of a second level of the map. The hardware assist circuit may be configured to search through the first level or any portions of the second level of the map in the cache in response to the start index, and notify the processor in response to the search detecting one or more blocks in the memory that contain valid data to be recycled.

Abstract: An apparatus having a processor and a circuit is disclosed. The processor is generally configured to initiate an operation to recycle a plurality of source blocks in a memory that is nonvolatile. The circuit is generally configured to (i) search through a first of a plurality of levels in a map that defines a plurality of translations between a plurality of logical addresses used at an interface to a computer and a plurality of physical addresses used in the memory and (ii) notify the processor in response to a detection in the first level of one or more of the source blocks to be recycled that contain valid data.

Abstract: A method for protecting data in a memory is disclosed. The method generally includes steps (A) to (D). Step (A) converts a logical address of one of a plurality of logical units to a physical address of a corresponding one of a plurality of physical units. Each physical unit is configured to store (i) data from a corresponding one of the logical units, (ii) respective error correction information and (iii) respective verification information. Step (B) writes a particular one of the physical units to the memory. Step (C) reads a portion of the particular physical unit from the memory. The portion includes the respective verification information. The respective verification information includes an indication of the logical address. Step (D) verifies the writing according to the respective verification information in the portion.

Abstract: An apparatus having a processor and a circuit is disclosed. The processor is generally configured to initiate an operation to recycle a plurality of source blocks in a memory that is nonvolatile. The circuit is generally configured to (i) search through a first of a plurality of levels in a map that defines a plurality of translations between a plurality of logical addresses used at an interface to a computer and a plurality of physical addresses used in the memory and (ii) notify the processor in response to a detection in the first level of one or more of the source blocks to be recycled that contain valid data.

Abstract: A method for protecting data in a memory is disclosed. The method generally includes steps (A) to (D). Step (A) converts a logical address of one of a plurality of logical units to a physical address of a corresponding one of a plurality of physical units. Each physical unit is configured to store (i) data from a corresponding one of the logical units, (ii) respective error correction information and (iii) respective verification information. Step (B) writes a particular one of the physical units to the memory. Step (C) reads a portion of the particular physical unit from the memory. The portion includes the respective verification information. The respective verification information includes an indication of the logical address. Step (D) verifies the writing according to the respective verification information in the portion.

Abstract: Device emulation implemented in programmable circuits. In one aspect, an interface for providing control of a hardware device includes functional code embedded in circuitry of the interface. Emulator code is embedded in programmable circuitry of the interface to emulate the hardware device during testing of the functional code and the interface. Another aspect diagnoses errors in a system having an interface and a connected hardware device, using emulator code embedded in a programmable circuit of the interface.

Abstract: A detoxification process for rendering three-dimensional objects formed by solid freeform fabrication techniques biocompatible for use in long-term dermal contact applications. The process nullifies cytotoxins normally present in objects formed by solid freeform fabrication techniques rendering such techniques as viable for the production of biocompatible devices such as stents, artery valve components, bone implant supports, pacemaker shells, surgical tools, and the like. In one embodiment, a custom hearing aid shell is produced by stereolithography from an acrylate photopolymer resin that was detoxified for long-term dermal contact application. The detoxification process makes three-dimensional objects created by solid freeform fabrication techniques available for products requiring biocompatibility.

Abstract: A method and apparatus for data transmission transmits both compressed and noncompressed data over each of a plurality of transmission paths. A data identification pattern is used to request a type of data from a memory having a plurality of data types stored within it. A handshaking control module is provided to select the correct type of data from the memory and place it on the output of the memory. The requested data type is then transmitted to a data decompression module via an interface. The data transmission can occur on any one of a plurality of data transmission paths when the data being transmitted is either Linework or Linework control data. When the data decompression module receives the data, it is then routed to any one of a plurality of data decompression systems based upon the results of the evaluation of the data identification pattern. The routing of the received data is wholly dependent upon the data identification pattern and independent of which transmission path the data was received on.

Abstract: A detoxification process for rendering three-dimensional objects formed by solid freeform fabrication techniques biocompatible for use in long-term dermal contact applications. The process nullifies cytotoxins normally present in objects formed by solid freeform fabrication techniques rendering such techniques as viable for the production of biocompatible devices such as stents, artery valve components, bone implant supports, pacemaker shells, surgical tools, and the like. In one embodiment, a custom hearing aid shell is produced by stereolithography from an acrylate photopolymer resin that was detoxified for long-term dermal contact application. The detoxification process makes three-dimensional objects created by solid freeform fabrication techniques available for products requiring biocompatibility.

Abstract: A detoxification process for rendering three-dimensional objects formed by solid freeform fabrication techniques biocompatible for use in long-term dermal contact applications. The process nullifies cytotoxins normally present in objects formed by solid freeform fabrication techniques rendering such techniques as viable for the production of biocompatible devices such as stents, artery valve components, bone implant supports, pacemaker shells, surgical tools, and the like. In one embodiment, a custom hearing aid shell is produced by stereolithography from an acrylate photopolymer resin that was detoxified for long-term dermal contact application. The detoxification process makes three-dimensional objects created by solid freeform fabrication techniques available for products requiring biocompatibility.

Abstract: An output interface allows a user circuit to access data for multiple objects in an interleaved fashion. Status information is provided to guarantee data availability before each transfer sequence is started. An identifier is provided for each object. Each identifier, after data transfer has ended, may be subsequently reused to identify a different object. The interface provides the ability to retrieve all data in an object or to cancel the object before reaching the end and discarding the unretrieved data. The objects are provided to the appropriate processing mechanisms within the printer to implement a printing task. These objects correspond to images and text to be printed on a page. Object data is temporarily stored in limited data memory of the memory system and object headers are stored in header memory before transfer via the output interface. Each object to be printed has an object header and may, or may not, have associated object data.