Abstract: A method comprising, introducing a dopant type into a semiconductor layer to define a well region of the semiconductor layer, the well region comprising a channel region, and introducing a dopant type into the well region to define a multiple implant region substantially coinciding with the well region but excluding the channel region.

Abstract: A substrate having semiconductor material and a surface that supports a gate electrode and defines a surface normal direction is provided. The substrate can include a drift region including a first dopant type. A well region can be disposed adjacent to the drift region and proximal to the surface, and can include a second dopant type. A termination extension region can be disposed adjacent to the well region and extend away from the gate electrode, and can have an effective concentration of second dopant type that is generally less than that in the well region. An adjust region can be disposed between the surface and at least part of the termination extension region. An effective concentration of second dopant type may generally decrease when moving from the termination extension region into the adjust region along the surface normal direction.

Abstract: A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

Abstract: A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

Abstract: There are provided semiconductor structures and devices comprising silicon carbide (SiC) and methods for making the same. The structures and devices comprise a base or shielding layer, channel and surface layer, all desirably formed via ion implantation. As a result, the structures and devices provided herein are hard, “normally off” devices, i.e., exhibiting threshold voltages of greater than about 3 volts.

Abstract: A crystalline composition is provided that includes gallium and nitrogen. The crystalline composition may have an amount of oxygen present in a concentration of less than about 3×1018 per cubic centimeter, and may be free of two-dimensional planar boundary defects in a determined volume of the crystalline composition. The volume may have at least one dimension that is about 2.75 millimeters or greater, and the volume may have a one-dimensional linear defect dislocation density of less than about 10,000 per square centimeter.

Abstract: A MOSFET device and a method for fabricating MOSFET devices are disclosed. The method includes providing a semiconductor device structure including a semiconductor device layer of a first conductivity type, and ion implanting a well structure of a second conductivity type in the semiconductor device layer, where the ion implanting includes providing a dopant concentration profile in a single mask implant sequence.

Abstract: A crystal comprising gallium nitride is disclosed. The crystal has at least one grain having at least one dimension greater than 2.75 mm, a dislocation density less than about 104 cm?2, and is substantially free of tilt boundaries.

Abstract: A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.

Abstract: A MOSFET device and a method for fabricating MOSFET devices are disclosed. The method includes providing a semiconductor device structure including a semiconductor device layer of a first conductivity type, and ion implanting a well structure of a second conductivity type in the semiconductor device layer, where the ion implanting includes providing a dopant concentration profile in a single mask implant sequence.

Abstract: A power electronic module includes: a switch module including a desaturation detection diode and a power semiconductor switch, and wherein the desaturation detection diode is coupled to a switching connection of the power semiconductor switch; and a driver module coupled to the switch module, wherein the driver module is configured for obtaining a voltage signal across the desaturation detection diode and the power semiconductor switch and configured for turning off the power semiconductor switch upon the voltage signal exceeding a threshold. In one example, the driver module is discrete from the switch module. In another example, the switch module and driver modules are configured to respectively provide and receive a voltage signal of less than or equal to seventy volts.

Abstract: A micro-electromechanical system (MEMS) switch array for power switching includes an input node, an output node, and a plurality of MEMS switches, wherein the input node and the output node are independently in electrical communication with a portion of the plurality of MEMS switches, and wherein a failure of any one of the plurality of MEMS switches does not render ineffective another MEMS switch within the MEMS switch array.

Abstract: A crystalline composition is provided. The crystalline composition may include gallium and nitrogen; and the crystalline composition may have an infrared absorption peak at about 3175 cm?1, with an absorbance per unit thickness of greater than about 0.01 cm?1.

Abstract: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.

Abstract: The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 ?m.

Abstract: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.

Abstract: A method of making a silicon carbide MOSFET is disclosed. The method includes providing a semiconductor device structure, wherein the device structure comprises a silicon carbide semiconductor device layer, an ion implanted well region of a first conductivity type formed in the semiconductor device layer, an ion implanted source region of a second conductivity type formed into the ion implanted well region; providing a mask layer over the semiconductor device layer, the mask layer exposing a portion of the ion implanted source region, then etching through the portion of the ion implanted source region to form a dimple; then implanting ions through the dimple to form a high dopant concentration first conductivity type ion implanted contact region, wherein the ion implanted contact region is deeper than the ion implanted well region; then removing the contact region mask layer and annealing implanted ions.

Abstract: An etchant including a halogenated salt, such as Cryolite (Na3AlF6) or potassium tetrafluoro borate (KBF4), is provided. The salt may be present in the etchant in an amount sufficient to etch a substrate and may have a melt temperature of greater than about 200 degrees Celsius. A method of wet etching may include contacting an etchant to at least one surface of a support layer of a multi-layer laminate, wherein the support layer may include aluminum oxide; or contacting an etchant to at least one surface of a support layer of a multi-layer laminate, wherein the etchant may include Cryolite (Na3AlF6), potassium tetrafluoro borate (KBF4), or both; and etching at least a portion of the support layer. The method may provide a laminate produced by growing a crystal onto an aluminum oxide support layer, and chemically removing at least a portion of the support layer by wet etch. An electronic device, optical device or combined device including the laminate is provided.

Abstract: A power electronic module includes: a switch module including a desaturation detection diode and a power semiconductor switch, and wherein the desaturation detection diode is coupled to a switching connection of the power semiconductor switch; and a driver module coupled to the switch module, wherein the driver module is configured for obtaining a voltage signal across the desaturation detection diode and the power semiconductor switch and configured for turning off the power semiconductor switch upon the voltage signal exceeding a threshold. In one example, the driver module is discrete from the switch module. In another example, the switch module and driver modules are configured to respectively provide and receive a voltage signal of less than or equal to seventy volts.

Abstract: One embodiment of the invention comprises a MEMS structure further comprising: a MEMS device (240) having a first surface with one or more contact structures (244, 245 and 246) thereon connected to functional elements of the MEMS device (240), a dielectric layer (100) overlying the first surface defining openings therein through which the contact structures (244, 245 and 246) are exposed, a patterned metallization layer (254, 255 and 256) comprising conductive material extending from the contact structures (244, 245 and 246) through the openings in the dielectric layer (100) and onto a surface of the dielectric layer and a first heat sink (190) in thermal communication with the metallization layer (254, 255 and 256).