Patents by Inventor Stephen Daley Arthur

Stephen Daley Arthur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080146004
    Abstract: A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.
    Type: Application
    Filed: December 13, 2006
    Publication date: June 19, 2008
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Kevin Sean Matocha, Vinayak Tilak, Stephen Daley Arthur, Zachary Matthew Stum
  • Publication number: 20080050876
    Abstract: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.
    Type: Application
    Filed: August 23, 2006
    Publication date: February 28, 2008
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Kevin Sean Matocha, Jody Alan Fronheiser, Larry Burton Rowland, Jesse Berkley Tucker, Stephen Daley Arthur, Zachary Matthew Stum
  • Patent number: 7175704
    Abstract: A method for removing defects at high pressure and high temperature (HP/HT) or for relieving strain in a non-diamond crystal commences by providing a crystal, which contains defects, and a pressure medium. The crystal and the pressure medium are disposed in a high pressure cell and placed in a high pressure apparatus, for processing under reaction conditions of sufficiently high pressure and high temperature for a time adequate for one or more of removing defects or relieving strain in the single crystal.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: February 13, 2007
    Assignee: Diamond Innovations, Inc.
    Inventors: Mark Philip D'Evelyn, Thomas Richard Anthony, Stephen Daley Arthur, Lionel Monty Levinson, John William Lucek, Larry Burton Rowland, Suresh Shankarappa Vagarali
  • Patent number: 7078731
    Abstract: A GaN crystal having up to about 5 mole percent of at least one of aluminum, indium, and combinations thereof. The GaN crystal has at least one grain having a diameter greater than 2 mm, a dislocation density less than about 104 cm?2, and is substantially free of tilt boundaries.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: July 18, 2006
    Assignee: General Electric Company
    Inventors: Mark Philip D'Evelyn, Dong-Sil Park, Steven Francis LeBoeuf, Larry Burton Rowland, Kristi Jean Narang, Huicong Hong, Stephen Daley Arthur, Peter Micah Sandvik
  • Publication number: 20040000266
    Abstract: A method for removing defects at high pressure and high temperature (HP/HT) or for relieving strain in a non-diamond crystal commences by providing a crystal, which contains defects, and a pressure medium. The crystal and the pressure medium are disposed in a high pressure cell and placed in a high pressure apparatus, for processing under reaction conditions of sufficiently high pressure and high temperature for a time adequate for one or more of removing defects or relieving strain in the single crystal.
    Type: Application
    Filed: June 5, 2003
    Publication date: January 1, 2004
    Inventors: Mark Philip D'Evelyn, Thomas Richard Anthony, Stephen Daley Arthur, Lionel Monty Levinson, John William Lucek, Larry Burton Rowland, Suresh Shankarappa Vagarali
  • Patent number: 5654226
    Abstract: A method of processing wafers for power devices in which the wafer has a desired thickness less than the thickness necessary to provide mechanical support. A silicon wafer of the desired thickness is bonded to a carrier wafer until most, if not all, of the processing steps are completed, after which the silicon wafer is separated from its carrier wafer. The carrier wafer may serve as a diffusion source, and the areas of the bonding of the silicon wafer to the carrier wafer may be selected consistent with the devices or groups of devices to be formed by the separation of the two wafers. The carrier wafer may by bonded to the device wafer over nearly the full surface area and the carrier wafer remain a part of the final device.
    Type: Grant
    Filed: September 7, 1994
    Date of Patent: August 5, 1997
    Assignee: Harris Corporation
    Inventors: Victor Albert Keith Temple, Stephen Daley Arthur