Patents by Inventor Stephen J. Rhodes

Stephen J. Rhodes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4698125
    Abstract: A method of producing a layered structure, the method including forming a spacer layer on a substrate, forming a parting layer on the spacer layer, forming a first masking pattern on the parting layer the first masking pattern delineating field regions in a first metal layer, etching the spacer layer and the parting layer in accordance with the first masking pattern, depositing a first metal layer, depositing an etch barrier layer, dissolving the parting layer to remove the masking pattern and the first metal layer and etch barrier layer in the field regions, depositing a passivation layer on the spacer layer, depositing a dielectric layer on the passivation layer, forming a second masking pattern on the dielectric layer, exposing the etch barrier layer in accordance with the second masking pattern, depositing a second metal layer, forming a third masking pattern on the second metal layer and etching the second metal layer in accordance with the third masking pattern.
    Type: Grant
    Filed: June 15, 1984
    Date of Patent: October 6, 1987
    Assignee: Plessey Overseas Limited
    Inventor: Stephen J. Rhodes
  • Patent number: 4536951
    Abstract: A method of forming a layered structure, which method comprises depositing a first metal layer on a substrate, depositing a barrier layer on the first metal layer, depositing a second metal layer on the barrier layer, forming a first masking pattern on the second metal layer, etching the first and second metal layers and the barrier layer in accordance with the first masking pattern, removing the first masking pattern, forming a second masking pattern on the second metal layer, etching the second metal layer in accordance with the second masking pattern, removing the second masking pattern, depositing a dielectric layer having a thickness sufficient to cover the second metal layer, etching the dielectric layer to expose the second metal layer, and depositing on the etched dielectric layer and exposed second metal layer a further metal layer to contact the exposed second metal layer.
    Type: Grant
    Filed: June 15, 1984
    Date of Patent: August 27, 1985
    Assignee: Plessey Overseas Limited
    Inventors: Stephen J. Rhodes, Raymond E. Oakley
  • Patent number: 4536249
    Abstract: An integrated circuit processing method comprises the formation on a substrate of a metallized conductor pattern. A layer of insulating material is formed over the conductor pattern and a mask is superimposed thereon. The mask is resistant to plasma etching and is provided at predetermined positions with apertures defining required void outlines. Plasma etching through the mask forms vias in the insulating layer which communicate with the metallized conductor pattern. The mask is removed to leave the integrated circuit with communicating vias which enable connection to the conductor pattern.
    Type: Grant
    Filed: April 6, 1984
    Date of Patent: August 20, 1985
    Assignee: Plessey Overseas Limited
    Inventor: Stephen J. Rhodes