Patents by Inventor Stephen J. Robinson

Stephen J. Robinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160170888
    Abstract: A first operation associated with a request for a page miss handler may be identified. A second operation associated with a current execution of the page miss handler may also be identified. An age of the first operation and an age of the second operation may be determined. The page miss handler may be interrupted based on the age of the first operation and the age of the second operation by stopping the current execution of the page miss handler for the second operation and starting execution of the page miss handler for the first operation.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 16, 2016
    Inventors: CHRISTOPHER D. BRYANT, STEPHEN J. ROBINSON
  • Publication number: 20150347168
    Abstract: In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if so, to re-map the access request to a virtual device page in a system memory associated with the VM, based at least in part on information stored in a control register of the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: August 14, 2015
    Publication date: December 3, 2015
    Inventors: Vedvyas Shanbhogue, Stephen J. Robinson
  • Patent number: 9189360
    Abstract: A method is described that involves referring to first information from a directory table in system memory. The first information includes location information and size information of a first slice of system memory where first tracing data is to be stored. The method also includes tracking the amount of tracing data stored in the first slice of system memory and comparing the amount against the size information. The method also includes, before the first slice of system memory is filled, referring to second information from the directory table in system memory, where, the second information includes location information and size information of a second slice of system memory where second tracing data is to be stored. The first slice is not contiguous with the second slice of system memory.
    Type: Grant
    Filed: June 15, 2013
    Date of Patent: November 17, 2015
    Assignee: Intel Corporation
    Inventors: Beeman C. Strong, Jason W. Brandt, Tsvika Kurts, Peter Lachner, Itamar Kazachinsky, Stephen J. Robinson, Peggy J. Irelan
  • Publication number: 20150277949
    Abstract: A processing system includes an interconnect and a processing core, coupled to the interconnect, to execute a plurality of virtual machines each being identified by a respective identifier, and tag, by an identifier of the first virtual machine, a first transaction initiated by a first virtual machine to access the interconnect.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: THIAM WAH LOH, GAUTHAM N. CHINYA, STEPHEN J. ROBINSON, REZA FORTAS, HONG WANG, HELMUT REINIG, PER HAMMARLUND, DEEPAK A. MATHAIKUTTY, CHRISTIAN ERBEN
  • Publication number: 20150278119
    Abstract: Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: THIAM WAH LOH, PER HAMMARLUND, ANDREAS WASSERBAUER, SWEE CHONG PETER KUAN, ECKHARD DELFS, DEEPAK A. MATHAIKUTTY, STEPHEN J. ROBINSON, GAUTHAM N. CHINYA, PERRY H. WANG, CHEE WENG TAN, HONG WANG, REZA FORTAS
  • Patent number: 9141570
    Abstract: In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if so, to re-map the access request to a virtual device page in a system memory associated with the VM, based at least in part on information stored in a control register of the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Stephen J. Robinson
  • Publication number: 20140372987
    Abstract: A method is described that involves referring to first information from a directory table in system memory. The first information includes location information and size information of a first slice of system memory where first tracing data is to be stored. The method also includes tracking the amount of tracing data stored in the first slice of system memory and comparing the amount against the size information. The method also includes, before the first slice of system memory is filled, referring to second information from the directory table in system memory, where, the second information includes location information and size information of a second slice of system memory where second tracing data is to be stored. The first slice is not contiguous with the second slice of system memory.
    Type: Application
    Filed: June 15, 2013
    Publication date: December 18, 2014
    Inventors: Beeman C. Strong, Jason W. Brandt, Tsvika Kurts, Peter Lachner, Itamar Kazachinsky, Stephen J. Robinson, Peggy J. Irelan
  • Publication number: 20140325110
    Abstract: In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if so, to re-map the access request to a virtual device page in a system memory associated with the VM, based at least in part on information stored in a control register of the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: July 15, 2014
    Publication date: October 30, 2014
    Inventors: Vedvyas Shanbhogue, Stephen J. Robinson
  • Publication number: 20140089616
    Abstract: In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if so, to re-map the access request to a virtual device page in a system memory associated with the VM, based at least in part on information stored in a control register of the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 27, 2014
    Inventors: Vedyvas Shanbhogue, Stephen J. Robinson
  • Publication number: 20140068230
    Abstract: A computer system and processor for elimination of move operations include circuits that obtain a computer instruction and bypass execution units in response to determining that the instruction includes a move operation that involves a transfer of data from a logical source register to a logical destination register. Instead of executing the move operation, the transfer of the data is performed by tracking changes in data dependencies of the source and the destination registers, and assigning a physical register associated with the source register to the destination register based on the dependencies.
    Type: Application
    Filed: October 4, 2012
    Publication date: March 6, 2014
    Inventors: Venkateswara Madduri, Jonathan Combs, James E. Phillips, Stephen J. Robinson, James D. Allen, Jonathan J. Tyler
  • Patent number: 8533721
    Abstract: A method and system to schedule out of order operations without the requirement to execute compare, ready and pick logic in a single cycle. A lazy out-of-order scheduler splits each scheduling loop into two consecutive cycles. The scheduling loop includes a compare stage, a ready stage and a pick stage. The compare stage and the ready stage are executed in a first of the two consecutive cycles and the pick stage is executed in a second of the two consecutive cycles. By splitting each scheduling loop into two consecutive cycles, selecting the oldest operation by default and checking the readiness of the oldest operation, it relieves the system of timing requirements and avoids the need for power hungry logic. Every execution of an operation does not appear as one extra cycle longer and the lazy out-of-order scheduler retains most of the performance of a full out-of-order scheduler.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: September 10, 2013
    Assignee: Intel Corporation
    Inventors: Stephen J. Robinson, Deepak Limaye
  • Publication number: 20110239218
    Abstract: A method and system to schedule out of order operations without the requirement to execute compare, ready and pick logic in a single cycle. A lazy out-of-order scheduler splits each scheduling loop into two consecutive cycles. The scheduling loop includes a compare stage, a ready stage and a pick stage. The compare stage and the ready stage are executed in a first of the two consecutive cycles and the pick stage is executed in a second of the two consecutive cycles. By splitting each scheduling loop into two consecutive cycles, selecting the oldest operation by default and checking the readiness of the oldest operation, it relieves the system of timing requirements and avoids the need for power hungry logic. Every execution of an operation does not appear as one extra cycle longer and the lazy out-of-order scheduler retains most of the performance of a full out-of-order scheduler.
    Type: Application
    Filed: March 26, 2010
    Publication date: September 29, 2011
    Inventors: Stephen J. Robinson, Deepak Limaye
  • Patent number: 5812091
    Abstract: An antenna array for radio interferometry uses three equi-spaced triplets set vertically above the ground with different respective spacings, the center antenna of each triplet being at a different height. Signal processing circuits provide for each triplet a signal which is a function of the elevation angle .theta. but is independent of the ground reflection coefficient, P. the signals are weighted to give the optimum value of .theta., e.g., by selecting the signal varying most rapidly with .theta.. Some antennae can be shared and for example three triplets may be provided by seven antenna elements.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: September 22, 1998
    Inventor: Stephen J. Robinson