Abstract: Some embodiments of a processing device include one or more power supply monitors to provide one or more counts representative of one or more operating frequencies of one or more circuit blocks based on a voltage supplied to the circuit block(s). Some embodiments of the processing device also include a system management unit to determine an initial voltage supplied to the circuit block(s) based on a target count and to reduce the voltage supplied to the circuit block(s) from the initial voltage in response to the count(s) generated by the power supply monitor(s) exceeding the target count.

Abstract: A circuit with headroom monitoring includes a memory array having memory cells, a replica array, and a built-in self test circuit. The replica array has a plurality of word lines, a plurality of bit line pairs, and memory cells located at intersections of the plurality of word lines and the plurality of bit line pairs. The memory cells are of a same type as memory cells in the memory array. The built-in self test circuit is coupled to the replica array for adding a capacitance to at least one bit line of the plurality of bit line pairs, for sensing a read time of memory cells of the replica array with the capacitance so added, and for providing a headroom signal in response to the read time.

Abstract: A method and apparatus is provided for monitoring performance of an processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor. In one example, the method and apparatus compares a measured value of an operating parameter (i.e., a temperature, supply voltage or clock signal) to predefined limits to identify an out of limits measured value. If an out of limits measured value is detected during a normal operating mode, the processor enters a reset mode, and if an out of limits measured value is detected during power up or reset, the processor in retained a reset mode.

Abstract: Some embodiments of a processing device include one or more power supply monitors to provide one or more counts representative of one or more operating frequencies of one or more circuit blocks based on a voltage supplied to the circuit block(s). Some embodiments of the processing device also include a system management unit to determine an initial voltage supplied to the circuit block(s) based on a target count and to reduce the voltage supplied to the circuit block(s) from the initial voltage in response to the count(s) generated by the power supply monitor(s) exceeding the target count.

Abstract: A circuit with headroom monitoring includes a memory array having memory cells, a replica array, and a built-in self test circuit. The replica array has a plurality of word lines, a plurality of bit line pairs, and memory cells located at intersections of the plurality of word lines and the plurality of bit line pairs. The memory cells are of a same type as memory cells in the memory array. The built-in self test circuit is coupled to the replica array for adding a capacitance to at least one bit line of the plurality of bit line pairs, for sensing a read time of memory cells of the replica array with the capacitance so added, and for providing a headroom signal in response to the read time.

Abstract: A method and apparatus is provided for monitoring performance of an processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor. In one example, the method and apparatus compares a measured value of an operating parameter (i.e., a temperature, supply voltage or clock signal) to predefined limits to identify an out of limits measured value. If an out of limits measured value is detected during a normal operating mode, the processor enters a reset mode, and if an out of limits measured value is detected during power up or reset, the processor in retained a reset mode.

Abstract: A circuit including is disclosed. The circuit includes a precharge circuit configured to pull a dynamic node toward a voltage present on the voltage supply node during a precharge phase, and an evaluation circuit configured to, during an evaluation phase, pull the dynamic node toward a ground voltage responsive to a first input condition and configured to inhibit pulling of the dynamic node down responsive to a second input condition. A pull-up circuit coupled between the first dynamic node and the voltage supply node includes first and second pull-up transistors. The first pull-up transistor is configured to activate responsive to the precharge phase. The second pull-up transistor is configured to activate at a delay time subsequent to entry of the evaluation phase. When the first and second pull-up transistors are active, a pull-up path is provided between the dynamic node and the voltage supply node.

Abstract: A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.

Abstract: The present invention provides an improved SRAM cell. Specifically, the present invention provides an SRAM cell having one or more sets of stacked transistors for isolating the cell during a read operation. Depending on the embodiment, the SRAM cell of the present invention can have eight or ten transistors. Regardless, the SRAM cell of the present invention typically includes separate/decoupled write word and read word lines, a pair of cross-coupled inverters, and a complimentary pair of pass transistors that are coupled to the write word line. Each set of stacked transistors implemented within the SRAM cell has a transistor that is coupled to a bit line as well as the read word line.

Abstract: A method, system and computer program product for modeling and simulating a powergated hierarchical element of an integrated circuit is disclosed. In modeling a powergated macro, the invention does not model all logic gates or elements as powergated, instead, the invention only models latches as connected to an integrated switch to be powergated. In addition, a fence circuit attached to the powergated macro is modeled as including an extra control signal to force a powergated state of the powergated macro into the fence circuit.

Abstract: A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge recycling means to turn on a switching means between a virtual ground and a ground, the charge recycling power gate including a first transistor, a virtual ground in signal communication with a first terminal of the first transistor, a ground in signal communication with a second terminal of the first transistor, a capacitor having a first terminal in signal communication with a third terminal of the first transistor and a second terminal in signal communication with the ground, and a second transistor having a first terminal in signal communication with the virtual ground and a second terminal in signal communication with the third terminal of the first transistor.

Abstract: Circuits and methods are provided to implement low voltage, higher performance semiconductor memory devices such as CMOS static random access memory (SRAM) or multi-port register files. For example, circuits and methods are provided for dynamically adjusting power supply and/or ground line voltages that are applied to the memory cells during different modes of memory operation to enable low voltage, high performance operation of the memory devices.

Abstract: A hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip is described. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.

Abstract: A method and apparatus for controlling power consumption by devices in an integrated circuit. The apparatus includes a complementary device for a corresponding device for which power consumption is desired to be reduced. The complementary device supports all or some of the tasks of the corresponding device. The complementary device receives tasks that can be executed by either itself or the corresponding device and based upon the power management scheme will either execute the task itself or allow the corresponding device.

Abstract: A test system and method for integrated circuits includes an energy source having an adjustable energy rate, and a feedback device, which measures a physical quantity at a discrete position on an integrated circuit. A control circuit adjusts the power source to externally apply energy to the integrated circuit at the discrete position. A circuit tester applies test programs to the integrated circuit while the discrete position is maintained at a value of the physical quantity in accordance with the control circuit.

Abstract: An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven with the small voltage swing, which is generated by small swing circuits. The integrated circuit further includes regeneration circuits, which are receiving small voltage swing inputs and are outputting first, or full voltage swings. The application of the small voltage swing to the signal lines saves power in the integrated circuit. A wide bandwidth, full-wordline I/O, memory integrated circuit has simultaneously operable connection paths between essentially all the memory cells that are attached to the same wordline and the corresponding I/O terminals, and it has a single ended data-line structure.

Abstract: A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge recycling means to turn on a switching means between a virtual ground and a ground, the charge recycling power gate including a first transistor, a virtual ground in signal communication with a first terminal of the first transistor, a ground in signal communication with a second terminal of the first transistor, a capacitor having a first terminal in signal communication with a third terminal of the first transistor and a second terminal in signal communication with the ground, and a second transistor having a first terminal in signal communication with the virtual ground and a second terminal in signal communication with the third terminal of the first transistor.

Abstract: This invention overcome the problems inherent in the prior art for increasing the performance of a register file that is constructed to include dual-Vt bitlines or single-Vt bitlines. The invention provides a boost of the drive signal for one of the transistors of a bitline circuit, preferably for the high voltage threshold read-selection transistor of a local bitline (LBL) circuit. The drive signal amplitude is made greater than the normal supply voltage by some increment delta V.

Abstract: A power saving cache and a method of operating a power saving cache. The power saving cache includes circuitry to dynamically reduce the logical size of the cache in order to save power. Preferably, a method is used to determine optimal cache size for balancing power and performance, using a variety of combinable hardware and software techniques. Also, in a preferred embodiment, steps are used for maintaining coherency during cache resizing, including the handling of modified (“dirty”) data in the cache, and steps are provided for partitioning a cache in one of several way to provide an appropriate configuration and granularity when resizing.

Abstract: Loadless 4T SRAM cells, and methods for operating such SRAM cells, which can provide highly integrated semiconductor memory devices while providing increased performance with respect to data stability and increased I/O speed for data access operations. A loadless 4T SRAM cell comprises a pair of access transistors and a pair of pull-down transistors, all of which are implemented as N-channel transistors (NFETs or NMOSFETS). The access transistors have lower threshold voltages than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “1” potential during standby. The pull-down transistors have larger channel widths as compared to the access transistors, which enables the SRAM cell to effectively maintain a logic “0” potential at a given storage node during a read operation.