Patents by Inventor Stephen M. Trimberger

Stephen M. Trimberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7968375
    Abstract: Method and apparatus for integrating capacitors in stacked integrated circuits are described. One aspect of the invention relates to a semiconductor assembly having a carrier substrate, a plurality of integrated circuit dice, and at least one metal-insulator-metal (MIM) capacitor. The integrated circuit dice are vertically stacked on the carrier substrate. Each MIM capacitor is disposed between a first integrated circuit die and a second integrated circuit die of the plurality of integrated circuit dice. The at least one MIM capacitor is fabricated on at least one of a face of the first integrated circuit die and a backside of the second integrated circuit die.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: June 28, 2011
    Assignee: XILINX, Inc.
    Inventors: Arifur Rahman, Stephen M. Trimberger
  • Patent number: 7949912
    Abstract: A system and method of securing data stored in a memory are disclosed. The method comprises storing a payload data in a memory in one of first and second states related by a transform, reading the payload data from the memory, attempting to use the payload data for an application, verifying the payload data as being in the first state, transforming the payload data as a function of the transform in response to verifying that the payload data is in the second state, and repeating performing the verifying and transforming steps until the payload data is verified as being in the first state.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: May 24, 2011
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7941673
    Abstract: An FPGA includes a plurality of configurable logic elements, a configuration circuit, a decryption circuit, and a fingerprint element. The fingerprint element generates a fingerprint that is indicative of inherent manufacturing process variations unique to the FPGA. The fingerprint is used as a key for an encryption system that protects against illegal use and/or copying of configuration data. In some embodiments, the propagation delay of various circuit elements formed on the FPGA are used to generate the fingerprint. In one embodiment, the specific frequency of an oscillator is used to generate the fingerprint. In some embodiments, a ratio of measurable values may be used to generate the fingerprint. In other embodiments, differences in transistor threshold voltages are used to generate the fingerprint. In still other embodiments, variations in line widths are used to generate the fingerprint.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: May 10, 2011
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7930661
    Abstract: A software model (620) of a stacked integrated circuit system (600) includes a first integrated circuit die (602) connected to a second integrated circuit die (604) through an interchip communication interface (606). A software model of the first integrated circuit die includes an integrated circuit resource (614) and an internal interface (150). A software model of the second integrated circuit die includes a stacked resource (618). The software model of the internal interface is configurable to connect the stacked resource of the second integrated circuit die to the integrated circuit resource through the interchip communication interface.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: April 19, 2011
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Arifur Rahman, Bernard J. New
  • Patent number: 7852701
    Abstract: A circuit structure for determining a period of time during which a device was without power is disclosed. The circuit structure comprises a volatile memory storing known data and a test circuit coupled to the volatile memory, the test circuit determining an amount of incorrect data stored in the volatile memory after a period of time during which the device was without power. The amount of incorrect data is used to determine the period of time during which the device was without power. A method of controlling a device based on the amount of incorrect data stored in a volatile memory after the device was without power is also disclosed. For example, the device can be controlled by altering a start-up sequence of one or more elements of the device.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: December 14, 2010
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7853916
    Abstract: Methods of using one of a plurality of configuration bitstreams in an integrated circuit are disclosed. An exemplary method comprises analyzing the plurality of implementations of a design to determine initial variations in timing among the implementations; modifying the implementations to reduce the variations in timing among the implementations; and outputting a plurality of configuration bitstreams for the implementations having variations in timing that are reduced relative to the initial variations in timing. Another method comprises generating a plurality of implementations for the design; generating a cost function for the design based upon costs (e.g.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: December 14, 2010
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Babak Ehteshami
  • Patent number: 7853799
    Abstract: A programmable encryption approach involves the use of a downloadable decryptor. According to an example embodiment of the present invention, an FPGA device includes a microcontroller for configuring logic circuitry on the FPGA device. A memory register is implemented for storing encryption key data and a message authentication code (MAC). When the FPGA device is to be configured using a configuration bitstream, a MAC is calculated for a decryptor and sent to the microcontroller along with an encryption key. The microcontroller stores the encryption key and MAC in a register to which access is limited. When the decryptor is downloaded to the microprocessor, a MAC is calculated on the downloaded decryptor and compared with the stored MAC. If the calculated MAC matches the stored MAC, the decryptor is allowed to access the key.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: December 14, 2010
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7849435
    Abstract: Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting user configuration bitstreams are stored along with associated test bitstreams in a memory device, e.g., a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the test bitstreams are loaded into a partially defective IC and tested using an automated testing procedure. When a test bitstream is found that enables the associated user design to function correctly in the programmed IC, i.e.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: December 7, 2010
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7831873
    Abstract: An integrated circuit is used to monitor and process parametric variations, such as temperature and voltage variations. An integrated circuit may include a temperature-sensitive oscillator circuit and a temperature-insensitive oscillator circuit, and frequency difference between the two sources may be monitored. In some embodiments, a parametric-insensitive reference oscillator is used as a reference to measure frequency performance of a second oscillator wherein the second oscillator performance is parametric-sensitive. The measured frequency performance is then compared to a tamper threshold and the result of the comparison is indicative of tampering.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: November 9, 2010
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Austin H. Lesea
  • Patent number: 7810059
    Abstract: Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams for a circuit design is disclosed. The method comprises analyzing a plurality of implementations for the circuit design; determining minimum timing constraints based upon all of the implementations for the circuit design; generating a representative implementation, based upon the plurality of implementations, which meets the determined minimum timing constraints for all of the implementations of the circuit design; and outputting the representative implementation.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: October 5, 2010
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7809544
    Abstract: Methods of detecting unwanted logic in a configuration bitstream for a programmable logic device (PLD). The bitstream can be reversed engineered to generate a model of the design. The model is then tested for unwanted logic, e.g., logic inserted for the purpose of monitoring or interfering with the desired functionality of the design, by applying a test suite that exercises all desired functions for the design. If some of the logic nodes in the model are not exercised by the test suite, then the unexercised nodes might constitute unwanted logic and might have been inserted for malicious purposes. To reverse engineer the bitstream, a simulation model of the unprogrammed PLD can be used. Configuration bits from the bitstream can be inserted into the model of the unprogrammed PLD. The modified model can be simplified by propagating constants through the model in response to the values inserted into the model.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: October 5, 2010
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7795901
    Abstract: A defect is automatically isolated in an integrated circuit device having programmable logic and interconnect circuits. A sequence of configurations is created to route data in a pattern through the programmable logic and interconnect circuits. Each configuration within the sequence is determined (e.g., generated or selected from a plurality of pre-generated configurations) as a function of output data from a prior configuration in the sequence. For each configuration in the sequence, the programmable logic and interconnect circuits are configured with the configuration and an automatic test instrument routes data in the pattern through the programmable logic and interconnect circuits. For each configuration in the sequence, the output data from the programmable logic and interconnect circuits is assessed. For each configuration in the sequence, the assessed output data isolates the defect to a portion of the pattern for the configuration that is within the portion for a prior configuration in the sequence.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: September 14, 2010
    Assignee: Xilinx, Inc.
    Inventors: Bobby Yang, Reto Stamm, Stephen M. Trimberger, Christopher H. Kingsley
  • Patent number: 7781879
    Abstract: Apparatus for integrating capacitors in stacked integrated circuits are described. One aspect of the invention relates to a semiconductor assembly having a carrier substrate, a plurality of integrated circuit dice, and at least one metal-insulator-metal (MIM) capacitor. The integrated circuit dice are vertically stacked on the carrier substrate. Each MIM capacitor is disposed between a first integrated circuit die and a second integrated circuit die of the plurality of integrated circuit dice. The at least one MIM capacitor is fabricated on at least one of a face of the first integrated circuit die and a backside of the second integrated circuit die.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: August 24, 2010
    Assignee: Xilinx, Inc.
    Inventors: Arifur Rahman, Stephen M. Trimberger
  • Patent number: 7747025
    Abstract: Decryptor is utilized in a dual role to maintain privacy of data decryption keys used in configuration bitstream decryption. In a first role, decryptor receives a data decryption key in an encrypted format (ENCRYPTED KEY DATA), which is then decrypted using a mask programmed decryption key. The decrypted key is then stored into one or more of key storage blocks. In a second role, decryptor is utilized to decrypt the encrypted configuration bitstream (ENCRYPTED CONFIGURATION DATA) using the previously decrypted data decryption key.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: June 29, 2010
    Assignee: XILINX, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7716497
    Abstract: An external storage device may transmit encrypted configuration data to a PLD during a configuration operation without transmitting the encryption key to the PLD and without retaining decryption information in the PLD. During a set-up operation, the encryption key is provided to the PLD, which generates an ID code upon power-up. The PLD generates a correction word in response to the encryption key and the ID code. The correction word is output from the PLD, which is powered-down, and is stored with the encrypted configuration data in the storage device. Then, during a configuration operation, the PLD is powered-on and re-generates the ID code. The correction word and the encrypted configuration data are transmitted to the PLD, which generates a decryption key in response to the re-generated ID code and the correction word.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: May 11, 2010
    Assignee: XILINX, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7701057
    Abstract: A semiconductor device having structures for reducing substrate noise coupled from through die vias (TDVs) is described. In one example, a semiconductor device has a substrate, at least one signal through die via (TDV), and ground TDVs. The substrate includes conductive interconnect formed on an active side thereof. The conductive interconnect includes ground conductors and digital signal conductors. Each signal TDV is formed in the substrate and is electrically coupled to at least one of the digital signal conductors. The ground TDVs are formed in the substrate in a ring around the at least one signal TDV. The ground TDVs are electrically coupled to the ground conductors. The ground TDVs provide a sink for noise coupled into the substrate from the signal TDVs. In this manner, the ground TDVs mitigate noise coupled to noise-sensitive components formed on the substrate.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: April 20, 2010
    Assignee: XILINX, Inc.
    Inventors: Arifur Rahman, Stephen M. Trimberger
  • Patent number: 7656189
    Abstract: Various approaches for detection of an unwanted function implemented in an integrated circuit (IC) are described. A controller is implemented on the IC, and at a first time while the IC is operating according to a circuit design, the controller reads a first data set from a subset of memory cells. The subset of memory cells stores state information of the circuit design. The controller determines whether the first data set is different from a second data set. In response to the first data set being different from the second data set, the controller outputs a threat signal that indicates the presence of unauthorized logic in the circuit design.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: February 2, 2010
    Assignee: XILINX, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7653820
    Abstract: A system for securely using decryption keys during FPGA configuration includes a FPGA having a microcontroller for receiving a bitstream having an encrypted bitstream portion as well as a configuration boot program. The configuration boot program can be code that runs on an embedded hardware microcontroller or a software microcontroller. The system further includes a key storage register coupled to the microcontroller for storing key data from the microcontroller, a decryptor coupled to the key storage register, and a configuration data register in the FPGA. Preferably, only the decryptor can read from the key storage register and the configuration data register cannot be read by the microcontroller after the decryptor is used.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: January 26, 2010
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7620863
    Abstract: Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting user configuration bitstreams are stored along with associated test bitstreams in a memory device, e.g., a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the test bitstreams are loaded into a partially defective IC and tested using an automated testing procedure. When a test bitstream is found that enables the associated user design to function correctly in the programmed IC, i.e.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: November 17, 2009
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7619438
    Abstract: Methods of enabling the use of defective programmable devices. The method comprises performing functional testing for each programmable device of a plurality of programmable devices; identifying each programmable device of the plurality of programmable devices having a defective portion of programmable blocks; identifying, for each programmable device which is identified to have a defective portion of programmable blocks, a location of the defective portion; and storing, for each programmable device which is identified to have a defective portion of programmable blocks, the location of the defective portion on the programmable device.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: November 17, 2009
    Assignee: XILINX, Inc.
    Inventor: Stephen M. Trimberger