Patents by Inventor Stephen M. Trimberger

Stephen M. Trimberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7605458
    Abstract: Method and apparatus for integrating capacitors in stacked integrated circuits are described. One aspect of the invention relates to a semiconductor assembly having a carrier substrate, a plurality of integrated circuit dice, and at least one metal-insulator-metal (MIM) capacitor. The integrated circuit dice are vertically stacked on the carrier substrate. Each MIM capacitor is disposed between a first integrated circuit die and a second integrated circuit die of the plurality of integrated circuit dice. The at least one MIM capacitor is fabricated on at least one of a face of the first integrated circuit die and a backside of the second integrated circuit die.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: October 20, 2009
    Assignee: XILINX, Inc.
    Inventors: Arifur Rahman, Stephen M. Trimberger
  • Patent number: 7607025
    Abstract: Methods of securing a programmable logic device (PLD) when an intrusion attempt is detected, e.g., methods of erasing sensitive data from the PLD or disabling configuration of the PLD in response to an attack. For example, when an attempt is made to configure the PLD with an unauthorized bitstream, a decryption key stored on the PLD can be erased, or decryption logic in the PLD can be otherwise disabled. The criteria for assuming that an attack is in progress can include, for example, the lack of a cyclic redundancy check (CRC) value included with a configuration bitstream, an attempt to operate the PLD outside normal operating ranges, receipt of an incorrect CRC value, or receipt of a predetermined number of bitstreams including incorrect CRC values. In some embodiments, an error correction procedure is performed on the bitstream, thereby preventing most transmission errors from being incorrectly interpreted as an attack.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: October 20, 2009
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7590956
    Abstract: Methods of detecting unwanted logic in an integrated circuit (IC) design. Any unwanted logic added to a design (e.g., to monitor or interfere with operation of the design) will draw power from one or more power supplies on the IC. Hence, by monitoring power drawn from various portions of a circuit design implemented in an IC, the unwanted logic can be detected and reported to the user. One way of monitoring power draw is by the use of oscillator circuits. If power goes down locally (e.g., due to the operation of unwanted logic), the frequency of an oscillator circuit in that vicinity will be reduced relative to the frequencies of other oscillator circuits in the design, and/or relative to an expected value. When a variation in the relative power consumption is detected, unwanted logic can be inferred and an error signal is output.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: September 15, 2009
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7523380
    Abstract: A random access memory (RAM) in a programmable logic device (PLD) supports error correction as well as a configurable data width. The number of bits in a user data word varies by the selected configuration of the RAM, while the number of bits in the error correction code (ECC) is unvarying, and is based on the total width of the memory. In some embodiments, separate ports are provided for the user data and the ECC data. Thus, ECC data can be written to an ECC portion of the RAM array at a given RAM address, while at the same time user data is written to or read from a configurable user data portion of the RAM array at the same RAM address. In other embodiments, a single memory access port is used for both user data and ECC data.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: April 21, 2009
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7518398
    Abstract: An integrated circuit with a through-die via (TDV) interface for die stacking is described. One aspect of the invention relates to an integrated circuit die having an array of tiles arranged in columns. The integrated circuit die includes at least one interface tile. Each interface tile includes a logic element, contacts, and through die vias (TDVs). The logic element is coupled to a routing fabric of the integrated circuit die. The contacts are configured to be coupled to conductive interconnect of another integrated circuit die attached to the backside of the integrated circuit die. The TDVs are configured to couple the logic element to the contacts.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: April 14, 2009
    Assignee: Xilinx, Inc.
    Inventors: Arifur Rahman, Stephen M. Trimberger, Bernard J. New
  • Patent number: 7482954
    Abstract: Method and apparatus for processing configuration data for a programmable logic device is described. The configuration data includes a sequence of frames. In one example, bits in the sequence of frames are identified as “don't care” bits that do not affect the functionality of a design implemented in the programmable logic device. Frames in the sequence of frames are compared to identify at least one set of identical frames, where the “don't care” bits are deemed to result in matches. Each of the at least one set of identical frames is merged to produce a respective at least one merged frame. Each of the at least one merged frame is associated with a plurality of configuration memory addresses in the programmable logic device. Each of the at least one merged frame may be loaded into configuration memory of the programmable logic device using a multi-frame write process.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: January 27, 2009
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7424655
    Abstract: Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting user configuration bitstreams are stored along with associated test bitstreams in a memory device, e.g., a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the test bitstreams are loaded into a partially defective IC and tested using an automated testing procedure. When a test bitstream is found that enables the associated user design to function correctly in the programmed IC, i.e.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: September 9, 2008
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7412635
    Abstract: Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting configuration bitstreams are stored in a memory device such as a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the various bitstreams are sequentially loaded into a partially defective IC and tested using an automated testing procedure. When a bitstream is found that enables the design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the automated testing procedure terminates, and the programmed IC begins to function according to the user design as determined by the last programmed bitstream.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: August 12, 2008
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7392500
    Abstract: Structures and methods that can be used to reduce power consumption in programmable logic devices (PLDs). Varying delays on the input paths of a PLD lookup table (LUT) can cause the nodes within the LUT (including the LUT output signal) to change state several times each time the input signals change state. Therefore, a programmable logic block for a PLD is provided that registers the LUT input signals instead of, or in addition to, the LUT output signal. The delays on the input paths are equalized and “glitching” on the LUT nodes is greatly reduced or eliminated. Thus, power consumption is reduced. Methods are also provided of reducing power consumption in PLDs by replacing single-bit registers on LUT output signals with multi-bit registers on LUT input signals, or by including multi-bit input registers in addition to the single-bit output registers.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: June 24, 2008
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7389429
    Abstract: Decryption keys used in decrypting encrypted configuration data for a programmable logic device are erased following decryption of encrypted configuration data. A self-erasing key memory delivers a decryption key to a programmable logic device and then automatically erases itself. The keys are then no longer available outside the programmable logic device.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: June 17, 2008
    Assignee: XILINX, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7380131
    Abstract: An FPGA includes a plurality of configurable logic elements, a configuration circuit, a decryption circuit, and a fingerprint element. The fingerprint element generates a fingerprint that is indicative of inherent manufacturing process variations unique to the FPGA. The fingerprint is used as a key for an encryption system that protects against illegal use and/or copying of configuration data. In some embodiments, the propagation delay of various circuit elements formed on the FPGA are used to generate the fingerprint. In one embodiment, the specific frequency of an oscillator is used to generate the fingerprint. In some embodiments, a ratio of measurable values may be used to generate the fingerprint. In other embodiments, differences in transistor threshold voltages are used to generate the fingerprint. In still other embodiments, variations in line widths are used to generate the fingerprint.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: May 27, 2008
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7373668
    Abstract: Described are methods and systems for encrypting and decrypting configuration data for programmable logic devices. An encrypted bitstream of configuration data includes two or more portions, each of which may be encrypted using a different key. Prior to loading, the author of each portion calculates the byte count for his or her portion and loads the required decryption key and byte count into a key and count memory. The designs are then loaded together as a single bitstream. The PLD decrypts the first portions using the first password. At the start of the partial bitstream, configuration logic loads the count associated with the decryption key for the first portions into a decrementing counter. The counter then decrements for each byte decrypted, reaching a count of zero when the first portion is fully decrypted. The configuration logic then selects the subsequent decryption key and associated count for the next portion of the bitstream.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: May 13, 2008
    Assignee: XILINX, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7366306
    Abstract: Described are programmable logic devices that decrypt proprietary configuration data using on-chip decryption keys. The keys are stored in a key memory that can be operated in a secure mode or a non-secure mode. The non-secure mode allows the decryption keys to be read or written freely; the secure mode bars read and write access to the decryption keys. The programmable logic device supports secure and non-secure modes on a key-by-key basis, allowing users to write, verify, and erase individual keys without affecting others.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: April 29, 2008
    Assignee: XILINX, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7365568
    Abstract: A circuit board includes a large scale logic device and at least one outrigger device wherein signals having a transmission delay budget that exceed a threshold value are produced to the outrigger device for coupling to circuit devices of the circuit board that are external to the large scale logic device. One embodiment of the invention comprises a plurality of outrigger devices that communicate with the large scale logic device by way of parallel data buses, as well as multi-gigabit transceiver data lines. Logic within the outrigger devices is generally limited to signal routing and transmission logic. The large scale logic device further comprises logic to transmit and receive signals to and from the outrigger devices in a way that is transparent to internal logic of the large scale logic device.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: April 29, 2008
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7353374
    Abstract: An integrated circuit (IC) with a supervisory control circuit is disclosed. In various embodiments, the IC includes a plurality of configurable logic resources and interconnection circuitry. A first interface circuit is coupled to a set of interface ports that are coupled to the interconnection circuitry, and a second interface circuit is coupled to the device management resources. A control store is configured with control codes for accessing the device management resources. Responsive to a command received via the first interface circuit, a control circuit is configured to fetch selected control codes from the control store, execute the control codes, and access a selected device management resource via the second interface circuit.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: April 1, 2008
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7328384
    Abstract: A method and apparatus that uses device defects as an identifier. Data is written to memory of an integrated circuit. Defects are identified based upon the writing of the data. An identifier for the IC is then derived using the identification of the defects.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: February 5, 2008
    Assignee: Xilinx, Inc.
    Inventors: Chidamber R. Kulkarni, Gary R. Lawman, Stephen M. Trimberger
  • Patent number: 7284229
    Abstract: Memory devices and data structures including multiple configuration bitstreams for programming integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting configuration bitstreams are stored in a memory device. Test bitstreams associated with the user bitstreams are optionally also included in the memory device. Under the control of a configuration control circuit, the various bitstreams are sequentially loaded into a partially defective IC and tested using an automated testing procedure. When a bitstream is found that enables the design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the configuration procedure terminates.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: October 16, 2007
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7278128
    Abstract: A method is disclosed for redeploying an FPGA that has been restricted for use with a first design. The FPGA accepts only those configuration bitstreams whose CRC checksums match a value stored on the FPGA. The restricted FPGA is used with a second configuration bitstream for a second design by altering the second configuration bitstream so that it generates a CRC checksum that matches the value stored on the FPGA. The first checksum is derived by applying a CRC hash function to the first configuration bitstream. The second configuration bitstream is altered so that the second checksum generated when the CRC hash function is applied to the altered second configuration bitstream is identical to the first checksum. Altering the second configuration bitstream can result in an altered second configuration bitstream that is either longer than or the same length as the second configuration bitstream.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: October 2, 2007
    Assignee: XILINX, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7269724
    Abstract: A method and apparatus are provided for updating or changing configuration data stored in the PROM of a target system, the data being used to configure one or more reprogrammable logic devices such as FPGAs. In one embodiment the apparatus comprises a modem used to communicate remotely with a host system, a shadow PROM for receiving new configuration data intended for use in a target system, an interface for relaying configuration data from the shadow PROM to the target, and means for controlling the components of the update system.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: September 11, 2007
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Robert O. Conn
  • Patent number: 7268581
    Abstract: A programmable logic device (PLD) includes a plurality of configurable resources, a programmable interconnect having a plurality of signal lines for providing a number of dedicated signal paths between any of the configurable resources, and a subway routing system having a shared subway bus coupled to the signal lines of the programmable interconnect at a plurality of connection points by a plurality of corresponding subway ports. The subway routing system, which provides alternate routing resources for the programmable interconnect, may be used to route different signals between different configurable resources at different times.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: September 11, 2007
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Austin H. Lesea