Abstract: This disclosure describes efficient transformation techniques that can be used in video coding. In particular, intermediate results of computations associated with transformation of a first block of video data are reused in the transformation of a second block of video data. The techniques may be used during a motion estimation process in which video blocks of a search space are transformed, but this disclosure is not necessarily limited in this respect. Pipelining techniques may be used to accelerate the efficient transformation techniques, and transposition memories can be implemented to facilitate efficient pipelining.

Abstract: This disclosure describes techniques for processing audio files that comply with the musical instrument digital interface (MIDI) format. In particular, various tasks associated with MIDI file processing are delegated between software operating on a general purpose processor, firmware associated with a digital signal processor (DSP), and dedicated hardware that is specifically designed for MIDI file processing. Alternatively, a multi-threaded DSP may be used instead of a general purpose processor and the DSP. In one aspect, this disclosure provides a method comprising parsing MIDI files and scheduling MIDI events associated with the MIDI files using a first process, processing the MIDI events using a second process to generate MIDI synthesis parameters, and generating audio samples using a hardware unit based on the synthesis parameters.

Abstract: This disclosure describes techniques for generating a set of data points that form a triangular wave having a desired gain and a desired frequency. In one example, the method includes the step of (a) determining an increment value based on the desired frequency and the desired gain of the triangular wave. The method further includes the step of (b) adding the increment value to a current data point to generate a next data point, the current data point and the next data point forming a subset of the set of data points. The method further includes the step of iteratively performing (a) and (b) to generate the set of data points that form the triangular wave.

Abstract: This disclosure describes techniques that make use of a waveform fetch unit that operates to retrieve waveform samples on behalf of each of a plurality of hardware processing elements that operate simultaneously to service various audio synthesis parameters generated from one or more audio files, such as musical instrument digital interface (MIDI) files. In one example, a method comprises receiving a request for a waveform sample from an audio processing element, and servicing the request by calculating a waveform sample number for the requested waveform sample based on a phase increment contained in the request and an audio synthesis parameter control word associated with the requested waveform sample, retrieving the waveform sample from a local cache using the waveform sample number, and sending the retrieved waveform sample to the requesting audio processing element.

Abstract: This disclosure describes techniques that make use of a plurality of hardware elements that operate simultaneously to service synthesis parameters generated from one or more audio files, such as musical instrument digital interface (MIDI) files. In one example, a method comprises storing audio synthesis parameters generated for one or more audio files of an audio frame, processing a first audio synthesis parameter using a first audio processing element of a hardware unit to generate first audio information, processing a second audio synthesis parameter using a second audio processing element of the hardware unit to generate second audio information, and generating audio samples for the audio frame based at least in part on a combination of the first and second audio information.

Abstract: A method for forming an output stream of data includes determining an output resolution for the output stream of data, determining an output frame rate for the output stream of data, determining an output color depth for the output stream of data, retrieving a first frame of data, a second frame of data, and a third frame of data from an input stream of data, the input stream of data having an input resolution, an input frame rate, and an input color depth, subsampling the first frame of data, the second frame of data, and the third frame of data to respectively form a first subsampled frame of data, a second subsampled frame of data, and a third subsampled frame of data, when the output resolution is lower than the input resolution, dropping the second subsampled frame of data, when the output frame rate is lower than the input frame rate, reducing color depth for the first subsampled frame of data and the second subsampled frame of data to respectively form a first reduced frame of data and a second reduced

Abstract: This disclosure describes efficient memory fetching techniques that can improve data fetching during a motion compensation decoding process. The techniques propose several different memory fetching modes that may be very efficient in different scenarios of the motion compensation decoding process. In some embodiments, a motion compensator selects a particular memory fetches associated with a motion compensation decoding process of a macroblock. The techniques described herein may be particularly useful when fractional interpolation to sub-integer pixels is used in the inter-frame compression.

Abstract: The disclosure describes image processing techniques useful for devices that support image processing of different sized images. The techniques can be used in many contexts, and may be particularly useful for front-end image processing of small viewfinder images and large still images captured by the device. In one embodiment, this disclosure provides a method comprising capturing a first image with a device, processing the first image using line buffers sized to accommodate an image width of the first image, and capturing a second image with the device, wherein the second image has an image width larger than the image width first image. The method also includes processing the vertical stripes of the second image using the line buffers, wherein the vertical stripes of the second image define widths that fit into the line buffers.

Abstract: This disclosure describes an organizational scheme for memory that is useful for image processing. A memory controller architecture is also described, which takes advantage of the organizational scheme. The organizational scheme and controller architecture is particularly useful for high performance, high quality image processing of images that form a video sequence, but may also be applied in other image processing settings. The described techniques and organizational structure of the memory also allows the memory to be shared for other storage applications of a video device.

Abstract: According to one embodiment, a circuit configured to form an output video stream includes a resolution modification circuit configured to receive a plurality of video frames from a frame buffer, and configured to modify resolution of the plurality of video frames, when the desired resolution for the output video stream is different than a resolution of the input video stream, the plurality of frames of data derived from an input video stream, a frame reducing circuit coupled to the resolution reducing circuit configured to reduce a number of video frames in the plurality of video frames from the resolution reducing circuit, when a desired frame rate for the output video stream is different than a frame rate of the input video stream, a depth reduction circuit coupled to the frame reducing circuit configured to reduce bit depth of the plurality of video frames from the frame reducing circuit, when a desired bit depth for the output video stream is different than a bit depth of the input video stream, and a rat

Abstract: According to one embodiment, a computer program product for a system including a processor includes a tangible memory including code that directs the processor to determine an output resolution for an output stream of data, code that directs the processor to determine an output frame rate for the output stream of data, code that directs the processor to determine an output color depth for the output stream of data, code that directs the processor to retrieve a first frame of data, a second frame of data, and a third frame of data from an input stream of data, the input stream of data having an input resolution, an input frame rate, and an input color depth, code that directs the processor to subsample the first frame of data, the second frame of data, and the third frame of data to respectively form a first subsampled frame of data, a second subsampled frame of data, and a third subsampled frame of data, when the output resolution is lower than the input resolution are also included, code that directs the pro

Abstract: This disclosure describes residual coding techniques that use vector quantization coding, which relies on template matching. However, rather than transmit vector quantization codebook indexes (or codewords) that may have no meaning to standard compliant CODECs, the techniques described herein map the residual templates to pre-computed compressed residual blocks that are compliant with a video standard. The standard compliant compressed residual blocks can then be transmitted to another device, which complies with the standard. The techniques can exploit the advantages associated with vector quantization coding, such as the ability to perform more parallel processing, while still maintaining compliance with a video coding standard.

Abstract: In one embodiment, this disclosure provides an encoding device comprising a mode selection engine that performs mode selection for intra-prediction encoding regardless of whether the encoding device is programmed to comply with first encoding standard or a second encoding standard. The device also includes a first encoder to perform the intra-prediction encoding according to the selected mode in compliance with the first encoding standard when the encoding device is programmed to comply with the first encoding standard, and a second encoder to perform the intra-prediction encoding according to the selected mode in compliance with the second encoding standard when the encoding device is programmed to comply with the second encoding standard. The techniques can simplify mode selection in support of multiple different intra-prediction encoding standards.

Abstract: This disclosure describes video encoding techniques and video encoding devices that implement such techniques. In one embodiment, this disclosure describes a video encoding device comprising a motion estimator that generates non-integer pixel values for motion estimation, the motion estimator including a filter that receives at least three inputs of integer pixel values. The video encoding device also comprises a memory that stores the non-integer pixel values generated by the motion estimator, and a motion compensator that uses the stored non-integer pixel values for motion compensation.

Abstract: A method and apparatus for motion compensation using a cache memory coupled to the motion compensation circuitry. The motion compensation method takes advantage of the fact that significant spatial overlap typically exists between a plurality of blocks that make up a macroblock in a motion estimation algorithm. Accordingly, a region of pixels may be stored in the cache memory and the cache memory may be repeatedly accessed to perform interpolation techniques on spatially adjacent blocks of data without having to access main memory, the latter being extremely inefficient and wasteful of memory bandwidth.

Abstract: This disclosure describes rate control techniques that can improve video encoding. In particular, the described rate control techniques exploit relationships between the number of bits encoded per frame and the number of non-zero coefficients of the video blocks after quantization. The number of number of non-zero coefficients of the video blocks after quantization is referred to as rho (?). The value of ? is generally proportional to the number of bits used in the video encoding. This disclosure utilizes a relationship between ? and a quantization parameter (QP) in order to achieve rate controlled video encoding. More specifically, this disclosure provides techniques for generating a lookup table (LUT) that maps values of ? to different QPs.

Abstract: A video encoder/decoder includes a vector pipeline unit and is configured only once by a processor to encode/decode data in accordance with any one of the JPEG, MPEG1, MPEG2 or MPEG4, H.261 or H.263 compression standards. The configuration data is stored in a configuration register of the video encoder/decoder. An optional ROM stores the configuration data for subsequent reading and loading—by the processor—into the configuration register. The vector pipeline unit includes: a run-length decoder, a binary arithmetic logic unit, a binary multiplier/divider, an accumulator, a barrel shifter, a round/modify unit, a saturate logic unit, a status register and a run-length encoder. Each component of the vector pipeline unit is optionally enabled or disabled. By disabling one or more components of the vector pipeline unit the power consumed by the encoder/decoder is reduced.

Abstract: A decoder for motion-picture-experts group (MPEG-4) video detects start codes at the beginning of video object planes (VOP) and resync markers at the start of each video packet (VP) in the VOP. When an error occurs in the bitstream, a parser searched for a next start code or resync marker to find the start of the next video packet. A partial match of the unique start-code bit sequence signals a fuzzy match, allowing the VOP header and data to be decoded even when bit errors occur in the VOP start code. A fuzzy match of the shorter resync marker can also be enabled. Fuzzy matching of VOP start codes and resync markers allows for faster recovery from corrupted bitstreams such as those transmitted over wireless networks.

Abstract: Error detection is added to a motion-picture-experts group (MPEG) decoder by checking each 8×8-pixel block for constraints. The constraints are added during compression by adjusting discrete cosine transform (DCT) coefficients in the block to meet a constraint. When the decoder determines that the constraint is not met by the DCT coefficients, an error is signaled for that block. The error can then be concealed using pixels from another frame or block. In one embodiment, the constraint is that the last two non-zero coefficients have the same magnitude. The constraint is added during compression after quantization but before variable-length coding by averaging the magnitudes and using the average magnitude for the last two non-zero coefficients. This minimizes visible distortion caused by the constraints and reduces computations.

Abstract: An apparatus may include a first plurality of registers, each register in the first plurality of registers configured to store data wordss, a first selector coupled to the first plurality of registers, the first selector configured to receive a data words stored in each register in the first plurality of registers, and configured to output the data words from a selected register from the first plurality of registers in response to a selection signal, a second plurality of registers, each register in the second plurality of registers configured to store a pointer associated with each register in the first plurality of registers, a second selector coupled to the second plurality of registers, the selector circuit configured to receive data from each register in the second plurality of registers, and configured to output data from a selected register from the second plurality of registers in response to the selection signal, the data comprising a pointer associated with the selected register from the first plura