Patents by Inventor Stephen S. Pawlowski
Stephen S. Pawlowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942175Abstract: Symbols interleaved among a set of codewords can provide an error correction/detection capability to a dual in-line memory module (DIMM) with memory chips having a comparatively larger bus width. Data corresponding to a set of multibit symbols and received from one or more memory devices can be interleaved/distributed with other bits of at least one codeword.Type: GrantFiled: July 27, 2022Date of Patent: March 26, 2024Assignee: Micron Technology, Inc.Inventors: Paolo Amato, Marco Sforzin, Stephen S. Pawlowski
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Publication number: 20240004799Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized as a plurality of channel groups. The memory controller comprises a plurality of memory access request/response buffer sets, and each memory access request/response buffer set of the plurality of memory access request/response buffer sets corresponds to a different one of the plurality of channel groups.Type: ApplicationFiled: May 26, 2023Publication date: January 4, 2024Inventors: Emanuele Confalonieri, Stephen S. Pawlowski, Patrick Estep
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Publication number: 20240004807Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The memory system with such memory units implemented can still provide a degree of data integrity and/or data authenticity required by standardized requirements and/or protocols, such as trusted execution engine security protocol (TSP).Type: ApplicationFiled: June 28, 2023Publication date: January 4, 2024Inventors: Paolo Amato, Marco Sforzin, Stephen S. Pawlowski
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Publication number: 20230418756Abstract: Systems, apparatuses, and methods related to a memory controller for cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache including a cache sequence controller configured to determine a quantity of a given type of result of cache look-up operations, determine the quantity satisfies a bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.Type: ApplicationFiled: June 27, 2023Publication date: December 28, 2023Inventors: Emanuele Confalonieri, Patrick Estep, Stephen S. Pawlowski, Nicola Del Gatto
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Publication number: 20230280940Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can include interface management circuitry coupled to a cache and a memory device. The memory controller can receive, by the interface management controller, a first signal indicative of data associated with a memory access request from a host. The memory controller can transmit a second signal indicative of the data to cache the data in a first location in the cache. The memory controller can transmit a third signal indicative of the data to cache the data in a second location in the cache.Type: ApplicationFiled: March 1, 2022Publication date: September 7, 2023Inventors: Nicola Del Gatto, Emanuele Confalonieri, Paolo Amato, Patrick Estep, Stephen S. Pawlowski
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Publication number: 20220359034Abstract: Symbols interleaved among a set of codewords can provide an error correction/detection capability to a dual in-line memory module (DIMM) with memory chips having a comparatively larger bus width. Data corresponding to a set of multibit symbols and received from one or more memory devices can be interleaved/distributed with other bits of at least one codeword.Type: ApplicationFiled: July 27, 2022Publication date: November 10, 2022Inventors: Paolo Amato, Marco Sforzin, Stephen S. Pawlowski
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Patent number: 11461011Abstract: The present disclosure techniques for implementing an apparatus, which includes processing circuitry that performs an operation based a target data block, a processor-side cache that implements a first cache line, memory-side cache that implements a second cache line having line width greater than the first cache line, and a memory array. The apparatus includes one or more memory controllers that, when the target data block results in a cache miss, determine a row address that identifies a memory cell row as storing the target data block, instruct the memory array to successively output multiple data blocks from the memory cell row to enable the memory-side cache to store each of the multiple of data blocks in the second cache line, and instruct the memory-side cache to output the target data block to a coherency bus to enable the processing circuitry to perform the operation based on the target data block.Type: GrantFiled: October 29, 2020Date of Patent: October 4, 2022Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Anton Korzh, Stephen S. Pawlowski
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Patent number: 11404136Abstract: Symbols interleaved among a set of codewords can provide an error correction/detection capability to a dual in-line memory module (DIMM) with memory chips having a comparatively larger bus width. Data corresponding to a set of multibit symbols and received from one or more memory devices can be interleaved/distributed with other bits of at least one codeword.Type: GrantFiled: December 16, 2020Date of Patent: August 2, 2022Assignee: Micron Technology, Inc.Inventors: Paolo Amato, Marco Sforzin, Stephen S. Pawlowski
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Publication number: 20220189574Abstract: Symbols interleaved among a set of codewords can provide an error correction/detection capability to a dual in-line memory module (DIMM) with memory chips having a comparatively larger bus width. Data corresponding to a set of multibit symbols and received from one or more memory devices can be interleaved/distributed with other bits of at least one codeword.Type: ApplicationFiled: December 16, 2020Publication date: June 16, 2022Inventors: Paolo Amato, Marco Sforzin, Stephen S. Pawlowski
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Patent number: 11086526Abstract: The present disclosure provides techniques for implementing a computing system that includes a processing sub-system, a memory sub-system, and one or more memory controllers. The processing sub-system includes processing circuitry that performs an operation based on a target data block and a processor-side cache coupled between the processing circuitry and a system bus. The memory sub-system includes a memory that stores data blocks in a memory array and a memory-side caches coupled between the memory channel and the system bus. The one or more memory controllers control caching in the processor-side cache based at least in part on temporal relationship between previous data block targeting by the processing circuitry and control caching in memory-side cache based at least in part on spatial relationship between data block storage locations in the memory channel.Type: GrantFiled: August 2, 2018Date of Patent: August 10, 2021Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Anton Korzh, Stephen S. Pawlowski
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Publication number: 20210048951Abstract: The present disclosure techniques for implementing an apparatus, which includes processing circuitry that performs an operation based a target data block, a processor-side cache that implements a first cache line, memory-side cache that implements a second cache line having line width greater than the first cache line, and a memory array. The apparatus includes one or more memory controllers that, when the target data block results in a cache miss, determine a row address that identifies a memory cell row as storing the target data block, instruct the memory array to successively output multiple data blocks from the memory cell row to enable the memory-side cache to store each of the multiple of data blocks in the second cache line, and instruct the memory-side cache to output the target data block to a coherency bus to enable the processing circuitry to perform the operation based on the target data block.Type: ApplicationFiled: October 29, 2020Publication date: February 18, 2021Inventors: Richard C. Murphy, Anton Korzh, Stephen S. Pawlowski
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Patent number: 10831377Abstract: The present disclosure provides techniques for implementing an apparatus, which includes processing circuitry that performs an operation based on target data block, a processor-side cache that implements a first cache line, memory-side cache that implements a second cache line having line width greater than the first cache line, and a memory array. The apparatus includes one or more memory controllers that, when the target data block results in a cache miss, determine a row address that identifies a memory cell row as storing the target data block, instruct the memory array to successively output multiple data blocks from the memory cell row to enable the memory-side cache to store each of the multiple data blocks in the second cache line, and instruct the memory-side cache to output the target data block to a coherency bus to enable the processing circuitry to perform the operation based on the target data block.Type: GrantFiled: May 27, 2020Date of Patent: November 10, 2020Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Anton Korzh, Stephen S. Pawlowski
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Publication number: 20200285400Abstract: The present disclosure provides techniques for implementing an apparatus, which includes processing circuitry that performs an operation based on target data block, a processor-side cache that implements a first cache line, memory-side cache that implements a second cache line having line width greater than the first cache line, and a memory array. The apparatus includes one or more memory controllers that, when the target data block results in a cache miss, determine a row address that identifies a memory cell row as storing the target data block, instruct the memory array to successively output multiple data blocks from the memory cell row to enable the memory-side cache to store each of the multiple data blocks in the second cache line, and instruct the memory-side cache to output the target data block to a coherency bus to enable the processing circuitry to perform the operation based on the target data block.Type: ApplicationFiled: May 27, 2020Publication date: September 10, 2020Inventors: Richard C. Murphy, Anton Korzh, Stephen S. Pawlowski
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Patent number: 10691347Abstract: The present disclosure techniques for implementing an apparatus, which includes processing circuitry that performs an operation based a target data block, a processor-side cache that implements a first cache line, memory-side cache that implements a second cache line having line width greater than the first cache line, and a memory array. The apparatus includes one or more memory controllers that, when the target data block results in a cache miss, determine a row address that identifies a memory cell row as storing the target data block, instruct the memory array to successively output multiple data blocks from the memory cell row to enable the memory-side cache to store each of the multiple of data blocks in the second cache line, and instruct the memory-side cache to output the target data block to a coherency bus to enable the processing circuitry to perform the operation based on the target data block.Type: GrantFiled: August 2, 2018Date of Patent: June 23, 2020Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Anton Korzh, Stephen S. Pawlowski
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Publication number: 20190377500Abstract: The present disclosure techniques for implementing a computing system that includes a processing sub-system, a memory sub-system, and one or more memory controllers. The processing sub-system includes processing circuitry that performs an operation based on a target data block and a processor-side cache coupled between the processing circuitry and a system bus. The memory sub-system includes a memory that stores data blocks in a memory array and a memory-side caches coupled between the memory channel and the system bus. The one or more memory controllers control caching in the processor-side cache based at least in part on temporal relationship between previous data block targeting by the processing circuitry and control caching in memory-side cache based at least in part on spatial relationship between data block storage locations in the memory channel.Type: ApplicationFiled: August 2, 2018Publication date: December 12, 2019Inventors: Richard C. Murphy, Anton Korzh, Stephen S. Pawlowski
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Publication number: 20190377679Abstract: The present disclosure techniques for implementing an apparatus, which includes processing circuitry that performs an operation based a target data block, a processor-side cache that implements a first cache line, memory-side cache that implements a second cache line having line width greater than the first cache line, and a memory array. The apparatus includes one or more memory controllers that, when the target data block results in a cache miss, determine a row address that identifies a memory cell row as storing the target data block, instruct the memory array to successively output multiple data blocks from the memory cell row to enable the memory-side cache to store each of the multiple of data blocks in the second cache line, and instruct the memory-side cache to output the target data block to a coherency bus to enable the processing circuitry to perform the operation based on the target data block.Type: ApplicationFiled: August 2, 2018Publication date: December 12, 2019Inventors: Richard C. Murphy, Anton Korzh, Stephen S. Pawlowski
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Patent number: 10146657Abstract: Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.Type: GrantFiled: March 26, 2014Date of Patent: December 4, 2018Assignee: Intel CorporationInventors: Robert C. Swanson, C. Brendan Traw, Vincent J. Zimmer, Mallik Bulusu, John R. Lindsley, Mahesh S. Natu, Dimitrios Ziakas, Robert W. Cone, Madhusudhan Rangarajan, Babak Nikjou, Kirk D. Brannock, Russell J. Wunderlich, Miles F. Schwartz, Stephen S. Pawlowski
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Patent number: 9547615Abstract: Systems and methods of operating a computing system may involve utilizing at least one of a peripheral protocol negotiation and a universal connector to determine a peripheral device protocol, and reconfiguring a computer device to accommodate that peripheral device protocol. Upon such a reconfiguration, the peripheral protocol negotiation may “step aside”, and one or more subsequent communications between a host computer and the peripheral device utilizing the peripheral device protocol may start.Type: GrantFiled: October 1, 2011Date of Patent: January 17, 2017Assignee: Intel CorporationInventors: Dennis M. Bell, Stephen S. Pawlowski
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Publication number: 20160117278Abstract: Systems and methods of operating a computing system may involve utilizing at least one of a peripheral protocol negotiation and a universal connector to determine a peripheral device protocol, and reconfiguring a computer device to accommodate that peripheral device protocol Upon such a reconfiguration, the peripheral protocol negotiation may “step aside”, and one or more subsequent communications between a host computer and the peripheral device utilizing the peripheral device protocol may start.Type: ApplicationFiled: October 1, 2011Publication date: April 28, 2016Inventors: Dennis M. Bell, Stephen S. Pawlowski
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Publication number: 20150278068Abstract: Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 26, 2014Publication date: October 1, 2015Inventors: Robert C. Swanson, C. Brendan Traw, Vincent J. Zimmer, Mallik Bulusu, John R. Lindsley, Mahesh S. Natu, Dimitrios Ziakas, Robert W. Cone, Madhusudhan Rangarajan, Babak Nikjou, Kirk D. Brannock, Russell J. Wunderlich, Miles F. Schwartz, Stephen S. Pawlowski