Patents by Inventor Stephen V. Kosonocky

Stephen V. Kosonocky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190319609
    Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Joyce Cheuk Wai WONG, Dragoljub IGNJATOVIC, Mikhail RODIONOV, Ljubisa BAJIC, Stephen V. KOSONOCKY, Steven J. KOMMRUSCH
  • Patent number: 10425089
    Abstract: A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A master oscillator circuit receives a regulated supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control a frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated supply voltage and a droopy supply voltage and supplies a slave oscillator signal having a frequency responsive to a slave frequency control signal that is based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to a voltage change of the droopy supply voltage.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 24, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephen V. Kosonocky, Mikhail Rodionov, Joyce C. Wong
  • Patent number: 10382014
    Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: August 13, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Joyce Cheuk Wai Wong, Dragoljub Ignjatovic, Mikhail Rodionov, Ljubisa Bajic, Stephen V. Kosonocky, Steven J. Kommrusch
  • Publication number: 20190199363
    Abstract: A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A master oscillator circuit receives a regulated supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control a frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated supply voltage and a droopy supply voltage and supplies a slave oscillator signal having a frequency responsive to a slave frequency control signal that is based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to a voltage change of the droopy supply voltage.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Stephen V. Kosonocky, Mikhail Rodionov, Joyce C. Wong
  • Publication number: 20190131928
    Abstract: A temperature sensor has a first transistor with a gate voltage tied to maintain the first transistor in an off state with leakage current flowing through the transistor, the leakage current varying with temperature. A second transistor is coupled to the first transistor and receives a gate voltage to keep the second transistor in an on state. A current mirror mirrors the leakage current and supplies a mirrored current used to control a frequency of an oscillator signal varies with the mirrored current. The temperature of the first transistor is determined based the frequency of the oscillator signal.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 2, 2019
    Inventors: Ravinder Reddy Rachala, Stephen V. Kosonocky
  • Patent number: 10247770
    Abstract: Various embodiments of a gate oxide breakdown detection technique detect gate oxide degradation due to stress on a per part basis without destroying functional circuits for an intended application. Stress on the gate oxide may be applied while nominal drain currents flow through a device, thereby stressing the device under conditions similar to actual operating conditions. The technique is relatively fast and does not require analog amplifiers or tuning of substantial amounts of other additional circuitry as compared to conventional gate oxide breakdown detection techniques.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: April 2, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Abhay Deshpande, Arun S. Iyer, Prasanth K. Vallur, Girish Anathahally Singrigowda, Stephen V. Kosonocky
  • Patent number: 10218273
    Abstract: A distributed voltage regulator has switches that function as resistors and are distributed in rows in a grid pattern across a regulated voltage domain. The switches receive an unregulated voltage and supply the regulated voltage. Switch control lines selectively enable the switches to achieve the desired voltage regulation. Droop detect circuits are also distributed through regulated voltage domain. The droop detect circuits detect when the regulated voltage is below a threshold and supply droop detect signals indicative thereof. A plurality of select circuits receive a first group of control lines to configure the switches for charge injection in response to a droop condition and a second group of control lines to configure the switches for other voltage regulation. The select circuits select one of the first and second group of control lines as switch control lines to configure the switches based on the droop detect signals.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 26, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Erhan Ergin, Dipanjan Sengupta, Elsie Lo, Stephen V. Kosonocky, Sree Rajesh Saha, Divya Guruja
  • Patent number: 10197455
    Abstract: A temperature dependent oscillator charges a capacitance from a voltage source through a switch. The switch is opened and the capacitance discharges through a transistor having a temperature dependent resistance. The voltage across the capacitance is compared to a predetermined threshold voltage. The comparator asserts a compare signal when the capacitance discharges to a predetermined voltage level. The switch is then closed for a long enough time to recharge the capacitor and then the switch is opened to allow the capacitance to discharge through the transistor. The charging and discharging repeats with a frequency that is exponentially related to temperature. A counter counts the oscillations over a predetermined time period. The count value is processed using a natural log function resulting in a thermal value corresponding to temperature. The thermal value may be corrected for supply voltage errors.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: February 5, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Stephen V. Kosonocky
  • Publication number: 20180374853
    Abstract: A distributed voltage regulator has switches that function as resistors and are distributed in rows in a grid pattern across a regulated voltage domain. The switches receive an unregulated voltage and supply the regulated voltage. Switch control lines selectively enable the switches to achieve the desired voltage regulation. Droop detect circuits are also distributed through regulated voltage domain. The droop detect circuits detect when the regulated voltage is below a threshold and supply droop detect signals indicative thereof. A plurality of select circuits receive a first group of control lines to configure the switches for charge injection in response to a droop condition and a second group of control lines to configure the switches for other voltage regulation. The select circuits select one of the first and second group of control lines as switch control lines to configure the switches based on the droop detect signals.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Inventors: Erhan Ergin, Dipanjan Sengupta, Elsie Lo, Stephen V. Kosonocky, Sree Rajesh Saha, Divya Guruja
  • Patent number: 10120430
    Abstract: A system and method for managing operating modes within a semiconductor chip for optimal power and performance while meeting a reliability target are described. A semiconductor chip includes a functional unit and a corresponding reliability monitor. The functional unit provides actual usage values to the reliability monitor. The reliability monitor determines expected usage values based on a reliability target and the age of the semiconductor chip. The reliability monitor compares the actual usage values and the expected usage values. The result of this comparison is used to increase or decrease current operational parameters.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: November 6, 2018
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Stephen V. Kosonocky, Thomas Burd, Adam Clark, Larry D. Hewitt, John Vincent Faricelli, John P. Petry
  • Publication number: 20180183413
    Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
    Type: Application
    Filed: December 23, 2016
    Publication date: June 28, 2018
    Inventors: Joyce Cheuk Wai Wong, Dragoljub Ignjatovic, Mikhail Rodionov, Ljubisa Bajic, Stephen V. Kosonocky, Steven J. Kommrusch
  • Publication number: 20180172753
    Abstract: Various embodiments of a gate oxide breakdown detection technique detect gate oxide degradation due to stress on a per part basis without destroying functional circuits for an intended application. Stress on the gate oxide may be applied while nominal drain currents flow through a device, thereby stressing the device under conditions similar to actual operating conditions. The technique is relatively fast and does not require analog amplifiers or tuning of substantial amounts of other additional circuitry as compared to conventional gate oxide breakdown detection techniques.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 21, 2018
    Inventors: Abhay Deshpande, Arun S. Iyer, Prasanth K. Vallur, Girish Anathahally Singrigowda, Stephen V. Kosonocky
  • Publication number: 20180067535
    Abstract: A system and method for managing operating modes within a semiconductor chip for optimal power and performance while meeting a reliability target are described. A semiconductor chip includes a functional unit and a corresponding reliability monitor. The functional unit provides actual usage values to the reliability monitor. The reliability monitor determines expected usage values based on a reliability target and the age of the semiconductor chip. The reliability monitor compares the actual usage values and the expected usage values. The result of this comparison is used to increase or decrease current operational parameters.
    Type: Application
    Filed: September 7, 2016
    Publication date: March 8, 2018
    Inventors: Stephen V. Kosonocky, Thomas Burd, Adam Clark, Larry D. Hewitt, John Vincent Faricelli, John P. Petry
  • Patent number: 9575553
    Abstract: A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: February 21, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Seng Oon Toh, Edward J. McLellan, Stephen V. Kosonocky, Michael Leonard Golden, Samuel D. Naffziger
  • Patent number: 9552892
    Abstract: A sampling circuit uses an input stage to sample an input signal and a secondary evaluation stage to maintain the output state of the input stage. Once the input stage transitions at a clock transition, the secondary evaluation stage uses regenerative feedback devices to hold the state to help ensure the sampling circuit only switches once during an evaluation.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: January 24, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephen V. Kosonocky, Krishnan T. Sukumar
  • Publication number: 20160341604
    Abstract: A temperature dependent oscillator charges a capacitance from a voltage source through a switch. The switch is opened and the capacitance discharges through a transistor having a temperature dependent resistance. The voltage across the capacitance is compared to a predetermined threshold voltage. The comparator asserts a compare signal when the capacitance discharges to a predetermined voltage level. The switch is then closed for a long enough time to recharge the capacitor and then the switch is opened to allow the capacitance to discharge through the transistor. The charging and discharging repeats with a frequency that is exponentially related to temperature. A counter counts the oscillations over a predetermined time period. The count value is processed using a natural log function resulting in a thermal value corresponding to temperature. The thermal value may be corrected for supply voltage errors.
    Type: Application
    Filed: May 19, 2015
    Publication date: November 24, 2016
    Inventor: Stephen V. Kosonocky
  • Patent number: 9405357
    Abstract: An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: August 2, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephen V. Kosonocky, Christopher Spence Oliver, Sudha Thiruvengadam, Carson D. Henrion
  • Publication number: 20160179186
    Abstract: A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: Seng Oon Toh, Edward J. McLellan, Stephen V. Kosonocky, Michael Leonard Golden, Samuel D. Naffziger
  • Patent number: 9300293
    Abstract: An integrated circuit device includes a first signal line for distributing a first signal. The first signal line includes a plurality of branch lines, and a leaf node is defined at an end of each branch line. First logic is coupled to the leaf nodes and operable to generate a first status signal indicative of a collective first logic state of the leaf nodes of the signal line corresponding to the first signal.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 29, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Donald A. Priore, John G. Petrovick, Jr., Stephen V. Kosonocky, Robert S. Orefice
  • Patent number: 9194914
    Abstract: Some embodiments of a power supply monitor include a measurement circuit to measure a voltage provided to the power supply monitor, a comparator to compare the voltage to a predetermined voltage threshold, and an interface to provide, during a scan test of a processing device including the power supply monitor, a fault signal in response to the voltage being below the voltage threshold. Some embodiments of a method include providing a first test pattern to one or more power supply monitors associated with one or more circuit blocks in the processing device and capturing a first result generated by the power supply monitor(s) based on the first test pattern. The first result indicates whether a voltage provided to the circuit block(s) is below a voltage threshold.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: November 24, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephen V. Kosonocky, Grady Giles