Patents by Inventor Stephen W. Bedell

Stephen W. Bedell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11068777
    Abstract: Controllable resistance elements and methods of setting the same include a junction field effect transistor configured to provide a resistance on a signal line. A first pass transistor is configured to apply a charge increment or decrement to the junction field effect transistor responsive to a control pulse, such that the resistance on the signal line changes.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Martin M. Frank, Devendra K. Sadana
  • Patent number: 11063161
    Abstract: A method of forming a photovoltaic device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 11062204
    Abstract: Methods of training a neural network include applying an input signal to an array of weights to generate weighted output signals based on resistances of respective weights in the array of weights. A difference between the weighted output signals and a predetermined expected output is determined. Weights in the array of weights are set by applying a pulse to a controllable resistance element in each weight. The pulse increments or decrements a charge on a junction field effect transistor in the respective controllable resistance element.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: July 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Martin M. Frank, Devendra K. Sadana
  • Patent number: 11055612
    Abstract: Neural networks include neuron layers arranged in order from an input neuron layer to an output neuron layer, with at least one hidden layer between them. Weight arrays between respective pairs of neuron layers each include controllable resistance elements and AND gates configured to control addressing of the plurality of controllable resistance elements. Each controllable resistance element includes a junction field effect transistor configured to provide a resistance on a signal line and a first pass transistor configured to apply a charge increment or decrement to the junction field effect transistor responsive to a control pulse, such that the resistance on the signal line changes. The control pulse is only passed to a controllable resistance element when a respective AND gate is triggered. A training module is configured to train the neural network by adjusting resistances of the plurality of controllable resistance elements in each of the weight arrays.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: July 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Martin M. Frank, Devendra K. Sadana
  • Publication number: 20210193897
    Abstract: A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.
    Type: Application
    Filed: March 5, 2021
    Publication date: June 24, 2021
    Inventors: Steven J. Holmes, Devendra V. Sadana, Ning Li, Stephen W. Bedell
  • Publication number: 20210184118
    Abstract: A bottom electrode is deposited on top of a substrate. A dielectric material layer is deposited on top of the bottom electrode. A hole is created in the dielectric material layer. A lift off layer is spun on and baked on the dielectric material layer. A photoresist layer is spun on and baked on the lift off layer. UV lithography is performed to create an opening above the hole in the dielectric material layer. An Ag layer is deposited on top of the remaining patterned dielectric material layer and the photoresist layer. A Germanium Antimony Telluride (GST) layer is deposited on top of the Ag layer. A top electrode is deposited on top of the GST layer. The Ag layer, the GST layer, and the top electrode located on top of the photoresist layer along with the photoresist layer and the lift off layer are removed.
    Type: Application
    Filed: December 11, 2019
    Publication date: June 17, 2021
    Inventors: Ning Li, Joel P. de Souza, Stephen W. Bedell, Devendra K. Sadana
  • Publication number: 20210151658
    Abstract: A method for fabricating an active cooling structure, comprising forming an array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer. The non-superconducting layer may comprise a plurality of non-superconducting traces running in a first direction. The superconductor layer may comprise a plurality of superconducting traces running in a second direction.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 20, 2021
    Inventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Ning Li
  • Publication number: 20210151653
    Abstract: An active cooling structure, comprising a non-superconducting layer, a superconducting layer, and an array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions. The non-superconducting layer may comprise a plurality of non-superconducting traces. The superconducting layer may comprise a plurality of superconducting traces. The array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions may be located between the plurality of non-superconducting traces and the plurality of superconducting traces.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 20, 2021
    Inventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Ning Li
  • Publication number: 20210151575
    Abstract: Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate a suspended Majorana fermion device comprising an ion implant defined nanorod in a semiconducting device are provided. According to an embodiment, a quantum computing device can comprise a Majorana fermion device coupled to an ion implanted region. The quantum computing device can further comprise an encapsulation film coupled to the ion implanted region and a substrate layer. The encapsulation film suspends the Majorana fermion device in the quantum computing device.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 20, 2021
    Inventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Patryk Gumann, Stephen W. Bedell, Ning Li
  • Publication number: 20210143417
    Abstract: A method of forming a solid-state lithium ion rechargeable battery may include depositing a metal layer onto a top surface of a substrate, depositing a handle layer onto a top surface of the metal layer, wherein a portion of the handle layer overlaps the metal layer and the substrate, spalling a portion of the substrate thereby forming a spalled substrate layer, porosifying the spalled substrate layer thereby forming a porous substrate layer, depositing an electrolyte layer onto a top surface of the porous substrate layer, wherein the electrolyte layer is in direct contact with the porous substrate layer, and depositing a cathode onto a top surface of the electrolyte layer. The method may include depositing a cathode contact layer onto a top surface of the cathode, wherein the cathode contact layer is in direct contact with the cathode. The porous substrate layer may be made of silicon.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Inventors: Devendra K. Sadana, Stephen W. Bedell, Joel P. de Souza, John COLLINS
  • Publication number: 20210143311
    Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A reflectrometry wire comprising a second metal within the reflectrometry region is formed. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Applicant: International Business Machines Corporation
    Inventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Ning Li, Stephen W. Bedell, Patryk Gumann
  • Publication number: 20210143310
    Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A sensing region gate is formed by coupling the semiconductor layer with a second metal layer. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Applicant: International Business Machines Corporation
    Inventors: Steven J. Holmes, Devendra K. Sadana, Sean Hart, Stephen W. Bedell, Ning Li, Patryk Gumann
  • Publication number: 20210143312
    Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of a first surface of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. The sensing region and a portion of the device region of the superconductor layer are exposed. A sensing region contact is formed by coupling the first surface of the semiconductor layer with a first metal layer. A nanorod contact using the first metal within the portion of the device region outside the sensing region is formed. By depositing a second metal layer on a second surface of the semiconductor layer within the sensing region, a tunnel junction gate is formed.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Applicant: International Business Machines Corporation
    Inventors: Steven J. Holmes, Stephen W. Bedell, Sean Hart, Devendra K. Sadana, Ning Li, Patryk Gumann
  • Publication number: 20210143325
    Abstract: A PCM cell is provided that includes a silver (Ag) doped Ge2Sb2Te5 (GST) alloy layer as the PCM material. The PCM cell containing the Ag doped GST alloy layer exhibits a reduced reset state resistance drift as compared to an equivalent PCM cell in which a non-Ag doped GST alloy layer is used. In some embodiments and depending on the Ag dopant concentration of the Ag doped GST alloy layer, a constant reset state resistance or even a negative reset state resistance drift can be obtained.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Inventors: Ning Li, Joel P. de Souza, Stephen W. Bedell, Devendra K. Sadana
  • Patent number: 11003942
    Abstract: A method for crystal analysis includes identifying a crystalline region on a device where an electronic channeling pattern is needed to be determined, acquiring a whole image for each of a plurality of different positions for the crystalline region using a scanning electron microscope (SEM) as the crystalline region is moved to different positions. Relevant regions are extracted from the whole images. The images of the relevant regions are stitched together to form a composite map of a full electron channeling pattern representative of the crystalline region wherein the electronic channeling pattern is provided due to an increase in effective angular range between a SEM beam and a surface of the crystal region.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Publication number: 20210135085
    Abstract: A deposition system includes a deposition source and a scanning stage disposed within a deposition path of the deposition source. The scanning stage includes a support platform configured to support a wafer thereon, and a mechanical actuator coupled to the support platform. The mechanical actuator is configured to translate the support platform with respect to the deposition source. The deposition system includes a proximity mask disposed within the deposition path of the deposition source between the deposition source and the scanning stage, the proximity mask defining a slit. The deposition system includes a controller in communication with the scanning stage, the controller configured to control the mechanical actuator to translate the wafer with respect to the slit such that an angle of deposition remains substantially constant. In operation, the proximity mask prevents deposition source material having a trajectory that is out of alignment with the slit from contacting the wafer.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Inventors: Stephen W. Bedell, Steven J. Holmes, Ning Li, Devendra K. Sadana
  • Publication number: 20210130944
    Abstract: In an embodiment, a fabrication method comprises forming first and second electrodes over a substrate that includes a nanowire that extends between, and beneath portions of, the first and second electrodes. The method also includes forming a mask structure that defines at least one opening over a portion of the nanowire and defines at least one overhang portion over a gap between the substrate and the mask. The method further includes depositing a first gate electrode on the substrate and overlapping a third region of the nanowire, and depositing a second gate electrode on the substrate and overlapping a fourth region of the nanowire. The depositing of the first gate electrode includes depositing conductive material through the at least one opening from a first oblique angle, and the depositing of the second gate electrode includes depositing conductive material through the at least one opening from a second oblique angle.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Applicant: International Business Machines Corporation
    Inventors: Steven J. Holmes, Devendra K. Sadana, Stephen W. Bedell, Ning Li
  • Patent number: 10978631
    Abstract: A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Devendra K. Sadana, Ning Li, Stephen W. Bedell
  • Patent number: 10971626
    Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: April 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
  • Patent number: 10957806
    Abstract: A method of forming a photovoltaic device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi