Patents by Inventor Stephen W. Bedell

Stephen W. Bedell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190252573
    Abstract: A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands to provide a textured surface of a photovoltaic device. A light emitting diode is formed on the textured surface of the photovoltaic device.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 10381479
    Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
  • Patent number: 10365240
    Abstract: A material removal process referred to as spalling is used to provide flexible and stretchable sensors that can be used for healthcare monitoring, bio-medical devices, wearable electronic devices, artificial skin, large area sensing, etc. The flexible and stretchable sensors of the present application have high sensitivity that is comparable to that of a bulk silicon sensor. The flexible and stretchable sensors comprise single crystalline spring-like structures that couple various resistor structures together.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Shu-Jen Han, Ning Li, Devendra K. Sadana
  • Patent number: 10355164
    Abstract: A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands to provide a textured surface of a photovoltaic device. A light emitting diode is formed on the textured surface of the photovoltaic device.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Publication number: 20190207000
    Abstract: An n-doped field effect transistor (nFET) section of an integrated device logic region is provided. The nFET section includes a semiconductor substrate, a layer at least partially formed of silicon germanium (SiGe) disposed on the semiconductor substrate and fin formations. The fin formations are formed on the layer. Each fin formation includes a first fin portion that is at least partially formed of silicon (Si) and a second fin portion that is at least partially formed of hard mask material. The layer is etched to include free surfaces that facilitate elastic relaxation of SiGe therein and a corresponding application of tension in Si of the first fin portion of each of the fin formations.
    Type: Application
    Filed: March 12, 2019
    Publication date: July 4, 2019
    Inventors: STEPHEN W. BEDELL, NICOLAS J. LOUBET, DEVENDRA K. SADANA
  • Publication number: 20190198696
    Abstract: A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 27, 2019
    Inventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20190186041
    Abstract: A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.
    Type: Application
    Filed: December 20, 2017
    Publication date: June 20, 2019
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Keith E. Fogel
  • Publication number: 20190183400
    Abstract: A cognitive urinary tract microcomputer is provided. The cognitive urinary tract microcomputer includes a propulsion device for moving the cognitive urinary tract microcomputer through a urinary tract. The cognitive urinary tract microcomputer further includes an image sensor for capturing images of the urinary tract. The cognitive urinary tract microcomputer also includes a computer having an image processor and a memory. The memory stores a cognitive algorithm executed by the image processor for comparing images of normal urinary tract segments to the captured images to detect abnormalities in the urinary tract and provide an indication of the abnormalities to a user.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 20, 2019
    Inventors: Hariklia Deligianni, Stephen W. Bedell, Bruce B. Doris
  • Publication number: 20190181951
    Abstract: A hybrid integrated circuit (HIC) with a high bandwidth, low-power, miniaturized, optically coupled data communication interface, the interface and an arrangement including the HIC. Active and passive components and integrated circuit (IC) chips may be mounted on an HIC substrate and collecting data. The HIC is smaller than one millimeter square and communicates data externally through a microLED (?LED) array mounted on the HIC substrate and coupled to other HIC components. Each “on” ?LED consumes less than ten microwatts (10 ?W).
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Inventors: Stephen W. Bedell, Devendra K. Sadana
  • Patent number: 10319893
    Abstract: Magnetic regions of at least one of chiplet or a receiving substrate are used to permit magnetically guided precision placement of chiplets on the receiving substrate. In some embodiments, a scanning magnetic head can be used to release individual chiplets from a temporary support substrate to the receiving substrate. Structures are provided in which a magnetic moment of a controlled orientation exists between the transferred chiplets and the receiving substrate.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bing Dang, Ning Li, Frank R. Libsch, Devendra K. Sadana
  • Patent number: 10304985
    Abstract: A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10304988
    Abstract: An electrical device that includes a material stack present on a supporting substrate. An LED is present in a first end of the material stack having a first set of bandgap materials. A photovoltaic device is present in a second end of the material stack having a second set of bandgap materials. The first end of the material stack being a light receiving end, wherein a widest bandgap material for the first set of bandgap material is greater than a highest bandgap material for the second set of bandgap materials.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 10304984
    Abstract: A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoar-Tabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10297665
    Abstract: An n-doped field effect transistor (nFET) section of an integrated device logic region is provided. The nFET section includes a semiconductor substrate, a layer at least partially formed of silicon germanium (SiGe) disposed on the semiconductor substrate and fin formations. The fin formations are formed on the layer. Each fin formation includes a first fin portion that is at least partially formed of silicon (Si) and a second fin portion that is at least partially formed of hard mask material. The layer is etched to include free surfaces that facilitate elastic relaxation of SiGe therein and a corresponding application of tension in Si of the first fin portion of each of the fin formations.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: May 21, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Nicolas J. Loubet, Devendra K. Sadana
  • Publication number: 20190148581
    Abstract: An electrical device that includes a material stack present on a supporting substrate. An LED is present in a first end of the material stack having a first set of bandgap materials. A photovoltaic device is present in a second end of the material stack having a second set of bandgap materials. The first end of the material stack being a light receiving end, wherein a widest bandgap material for the first set of bandgap material is greater than a highest bandgap material for the second set of bandgap materials. A zinc oxide interface layer is present between the LED and the photovoltaic device. The zinc oxide layers or can also form a LED.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 16, 2019
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Publication number: 20190130259
    Abstract: Neural networks include neuron layers arranged in order from an input neuron layer to an output neuron layer, with at least one hidden layer between them. Weight arrays between respective pairs of neuron layers each include controllable resistance elements and AND gates configured to control addressing of the plurality of controllable resistance elements. Each controllable resistance element includes a junction field effect transistor configured to provide a resistance on a signal line and a first pass transistor configured to apply a charge increment or decrement to the junction field effect transistor responsive to a control pulse, such that the resistance on the signal line changes. The control pulse is only passed to a controllable resistance element when a respective AND gate is triggered. A training module is configured to train the neural network by adjusting resistances of the plurality of controllable resistance elements in each of the weight arrays.
    Type: Application
    Filed: December 26, 2018
    Publication date: May 2, 2019
    Inventors: Stephen W. Bedell, Martin M. Frank, Devendra K. Sadana
  • Publication number: 20190128841
    Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.
    Type: Application
    Filed: December 13, 2018
    Publication date: May 2, 2019
    Inventors: Ali Afzali-Ardakani, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 10276739
    Abstract: An electrical device that includes a material stack present on a supporting substrate. An LED is present in a first end of the material stack having a first set of bandgap materials. A photovoltaic device is present in a second end of the material stack having a second set of bandgap materials. The first end of the material stack being a light receiving end, wherein a widest bandgap material for the first set of bandgap material is greater than a highest bandgap material for the second set of bandgap materials.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Publication number: 20190115485
    Abstract: A photodiode fabricated using spalling techniques, and method for making the same. The photodiode including a substrate, an optical device semiconductor material layer disposed over the substrate, a p-type contact disposed over the optical device semiconductor material layer, an n-type contact disposed over the substrate, and an adhesion layer for rear illumination adhered to the bottom of the substrate. Both the substrate and the optical device semiconductor material layer comprise at least one of GaN, AlGaN or AlN.
    Type: Application
    Filed: October 18, 2017
    Publication date: April 18, 2019
    Inventors: Stephen W. BEDELL, James R. KOZLOSKI, Devendra K. SADANA
  • Patent number: 10256357
    Abstract: A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi